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authorAlex Deucher <alexdeucher@gmail.com>2010-03-17 19:50:59 -0400
committerDave Airlie <airlied@redhat.com>2010-03-31 13:11:23 +1000
commitc1bcad9d16831859373d8f579fa1e146409f9960 (patch)
tree46ae3fb1634b8808e017f4c9a015542624604156 /drivers/gpu/drm/radeon/atombios_crtc.c
parentb2f8ccd84059f7d0c3e4f67d577abca391bc1868 (diff)
drm/radeon/kms: remove lvds quirks
- no longer needed with the latest new pll algo fixes. - also don't use lcd pll limits. They don't seem to work well for all systems. If we have a case where they are useful, we can set the flag for that case. fixes fdo bug 27083 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 7c30e2e74c8..94aa6b293e0 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -521,12 +521,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
adjusted_clock = mode->clock * 2;
- /* LVDS PLL quirks */
- if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
- struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
- pll->algo = dig->pll_algo;
- pll->flags |= RADEON_PLL_IS_LCD;
- }
} else {
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;