diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2014-11-07 12:51:04 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-11-12 11:56:39 -0500 |
| commit | 21b8a369046fbccb39f66cf065c43289376e63fa (patch) | |
| tree | 6de7d8a2e18906d98eca18c3e6e6eeb3ecf30a67 /drivers/gpu/drm/radeon/ci_dpm.c | |
| parent | 1c52279f578f8d1dc164c0d27f8f00b5aa06f2c1 (diff) | |
drm/radeon: fix dram timing for certain hawaii boards
Certain memory configurations need a fix.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ci_dpm.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/ci_dpm.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 893ed68cbae..4dd8f357523 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -2071,6 +2071,33 @@ static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); } +static void ci_register_patching_mc_arb(struct radeon_device *rdev, + const u32 engine_clock, + const u32 memory_clock, + u32 *dram_timimg2) +{ + bool patch; + u32 tmp, tmp2; + + tmp = RREG32(MC_SEQ_MISC0); + patch = ((tmp & 0x0000f00) == 0x300) ? true : false; + + if (patch && + ((rdev->pdev->device == 0x67B0) || + (rdev->pdev->device == 0x67B1))) { + if ((memory_clock > 100000) && (memory_clock <= 125000)) { + tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; + *dram_timimg2 &= ~0x00ff0000; + *dram_timimg2 |= tmp2 << 16; + } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { + tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; + *dram_timimg2 &= ~0x00ff0000; + *dram_timimg2 |= tmp2 << 16; + } + } +} + + static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, u32 sclk, u32 mclk, @@ -2086,6 +2113,8 @@ static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; + ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2); + arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); arb_regs->McArbBurstTime = (u8)burst_time; |