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authorAlex Deucher <alexander.deucher@amd.com>2013-06-25 17:56:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 19:40:05 -0400
commita9e61410921bcc1aa8f594ffa6301d5baba90f3b (patch)
tree82c267bd9854a8d0cb7b3a8ccc8693194ecfd236 /drivers/gpu/drm/radeon/ni_dpm.h
parenta0ceada6b4da18e8539bc3229adae3dc9b05d9a2 (diff)
drm/radeon/kms: add dpm support for SI (v7)
This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ni_dpm.h')
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/ni_dpm.h b/drivers/gpu/drm/radeon/ni_dpm.h
index 59c1692f783..887442497bf 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.h
+++ b/drivers/gpu/drm/radeon/ni_dpm.h
@@ -231,4 +231,11 @@ struct ni_power_info {
#define NISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
#define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
+int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
+ u32 arb_freq_src, u32 arb_freq_dest);
+void ni_update_current_ps(struct radeon_device *rdev,
+ struct radeon_ps *rps);
+void ni_update_requested_ps(struct radeon_device *rdev,
+ struct radeon_ps *rps);
+
#endif