diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-11-23 00:41:00 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-11-26 10:42:05 +1000 |
| commit | acb325062afc09c196f7d3888b81312e6ebcdc35 (patch) | |
| tree | 5c61abac0be07055b726b4c54caaa86ef4f32f4b /drivers/gpu/drm/radeon/r100.c | |
| parent | b6724405bc67ef3ae1318002085cde382b12345f (diff) | |
drm/radeon/kms: improve pflip precision on r1xx-r4xx
The update pending bit has a separate enable bit.
Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 2316f73db6c..300b4a64d8f 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -76,6 +76,8 @@ void r100_pre_page_flip(struct radeon_device *rdev, int crtc) /* make sure flip is at vb rather than hb */ tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset); tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; + /* make sure pending bit is asserted */ + tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp); /* set pageflip to happen as late as possible in the vblank interval. @@ -104,9 +106,9 @@ u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) /* update the scanout addresses */ WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); - /* Note: We don't wait for update_pending to assert, as this never - * happens for some reason on R1xx - R4xx. Adds a bit of imprecision. - */ + /* Wait for update_pending to go high. */ + while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)); + DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); /* Unlock the lock, so double-buffering can take place inside vblank */ tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; |