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| author | Robert Richter <robert.richter@amd.com> | 2008-09-24 11:25:31 +0200 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2008-09-24 11:25:31 +0200 |
| commit | f78e80209cf143be49f268c340431ae9fa3abb74 (patch) | |
| tree | 820fa64b688099dfdd93d27ba03252738ca5c7e2 /drivers/gpu/drm/radeon/r300_reg.h | |
| parent | 4c168eaf7ea39f25a45a3d8c7eebc3fedb633a1d (diff) | |
| parent | 24342c34a022ee90839873d91396045e12ef1090 (diff) | |
Merge commit 'v2.6.27-rc5' into tip/oprofile
Conflicts:
arch/x86/oprofile/nmi_int.c
Diffstat (limited to 'drivers/gpu/drm/radeon/r300_reg.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/r300_reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h index a6802f26afc..ee6f811599a 100644 --- a/drivers/gpu/drm/radeon/r300_reg.h +++ b/drivers/gpu/drm/radeon/r300_reg.h @@ -317,7 +317,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and * avoids bugs caused by still running shaders reading bad data from memory. */ -#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 /* Absolutely no clue what this register is about. */ #define R300_VAP_UNKNOWN_2288 0x2288 @@ -513,7 +513,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* gap */ /* Zero to flush caches. */ -#define R300_TX_CNTL 0x4100 +#define R300_TX_INVALTAGS 0x4100 #define R300_TX_FLUSH 0x0 /* The upper enable bits are guessed, based on fglrx reported limits. */ @@ -1362,6 +1362,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ +#define R300_RB3D_AARESOLVE_CTL 0x4E88 /* gap */ /* Guess by Vladimir. |