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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-10-08 12:02:06 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-10-08 12:02:06 -0700 |
| commit | 1c6e6d91b22c4271e8a5dab559a08cb005a77073 (patch) | |
| tree | 2801132011569f0635b896cde16a1e9c2db3acdf /drivers/gpu/drm/radeon/r420d.h | |
| parent | d8e7b2b3ac5319fcee616488c628c2bbe7e2937b (diff) | |
| parent | c1176d6f03e1085797ce83648a2c76ae15a2b515 (diff) | |
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (24 commits)
drm/radeon/kms: fix vline register for second head.
drm/r600: avoid assigning vb twice in blit code
drm/radeon: use list_for_each_entry instead of list_for_each
drm/radeon/kms: Fix AGP support for R600/RV770 family (v2)
drm/radeon/kms: Fallback to non AGP when acceleration fails to initialize (v2)
drm/radeon/kms: Fix RS600/RV515/R520/RS690 IRQ
drm/radeon: Fix setting of bits
drm/ttm: fix refcounting in ttm global code.
drm/fb: add more correct 8/16/24/32 bpp fb support.
drm/fb: add setcmap and fix 8-bit support.
drm/radeon/kms: respect single crtc cards, only create one crtc. (v2)
drm: Delete the DRM_DEBUG_KMS in drm_mode_cursor_ioctl
drm/radeon/kms: add support for "Surround View"
drm/radeon/kms: Fix irq handling on AVIVO hw
drm/radeon/kms: R600/RV770 remove dead code and print message for wrong BIOS
drm/radeon/kms: Fix R600/RV770 disable acceleration path
drm/radeon/kms: Fix R600/RV770 startup path & reset
drm/radeon/kms: Fix R600 write back buffer
drm/radeon/kms: Remove old init path as no hw use it anymore
drm/radeon/kms: Convert RS600 to new init path
...
Diffstat (limited to 'drivers/gpu/drm/radeon/r420d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/r420d.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h index a48a7db1e2a..fc78d31a0b4 100644 --- a/drivers/gpu/drm/radeon/r420d.h +++ b/drivers/gpu/drm/radeon/r420d.h @@ -212,9 +212,9 @@ #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) #define C_00000D_FORCE_E2 0xFFEFFFFF -#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) -#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) -#define C_00000D_FORCE_SE 0xFFDFFFFF +#define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21) +#define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1) +#define C_00000D_FORCE_VAP 0xFFDFFFFF #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) #define C_00000D_FORCE_IDCT 0xFFBFFFFF @@ -224,24 +224,24 @@ #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) #define C_00000D_FORCE_RE 0xFEFFFFFF -#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) -#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) -#define C_00000D_FORCE_PB 0xFDFFFFFF +#define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25) +#define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1) +#define C_00000D_FORCE_SR 0xFDFFFFFF #define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) #define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) #define C_00000D_FORCE_PX 0xFBFFFFFF #define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) #define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) #define C_00000D_FORCE_TX 0xF7FFFFFF -#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) -#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) -#define C_00000D_FORCE_RB 0xEFFFFFFF +#define S_00000D_FORCE_US(x) (((x) & 0x1) << 28) +#define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1) +#define C_00000D_FORCE_US 0xEFFFFFFF #define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29) #define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1) #define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF -#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30) -#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1) -#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF +#define S_00000D_FORCE_SU(x) (((x) & 0x1) << 30) +#define G_00000D_FORCE_SU(x) (((x) >> 30) & 0x1) +#define C_00000D_FORCE_SU 0xBFFFFFFF #define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31) #define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1) #define C_00000D_FORCE_OV0 0x7FFFFFFF |