diff options
| author | Marek Olšák <maraeo@gmail.com> | 2012-03-08 00:56:00 +0100 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2012-03-20 08:44:12 +0000 |
| commit | 779923bc40e123976bb0bee07b1c6a47d2858137 (patch) | |
| tree | 9e4118055cc0baf8ef04c1bc6381cafcc6fa3cc1 /drivers/gpu/drm/radeon/r600_cs.c | |
| parent | 9c1dfc5574a7f7115c0fe5bd8f838a8b7a52ee6d (diff) | |
drm/radeon/kms: skip cb/db checking if SX_MISC is 1 on r600+
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_cs.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 2e465a7089b..b3c40e0fe7e 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -74,6 +74,7 @@ struct r600_cs_track { u32 db_offset; struct radeon_bo *db_bo; u64 db_bo_mc; + bool sx_misc_kill_all_prims; }; #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } @@ -322,6 +323,7 @@ static void r600_cs_track_init(struct r600_cs_track *track) track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; } + track->sx_misc_kill_all_prims = false; } static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) @@ -479,6 +481,9 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) } } + if (track->sx_misc_kill_all_prims) + return 0; + /* check that we have a cb for each enabled target, we don't check * shader_mask because it seems mesa isn't always setting it :( */ @@ -1279,6 +1284,9 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) } ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); break; + case SX_MISC: + track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; + break; default: dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); return -EINVAL; |