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authorDave Airlie <airlied@redhat.com>2010-03-01 15:41:26 +1000
committerDave Airlie <airlied@redhat.com>2010-03-01 15:41:26 +1000
commitcf7934a2a0ec55759fcf6861a868baadfd522300 (patch)
tree97fb4aac01d1b4e112126b2bd3852e3646d4b408 /drivers/gpu/drm/radeon/radeon_drv.h
parentaa71fa3cd5b7b4f669cd74c5a16de57d2938cd85 (diff)
parent6070a4a928f8c92b9fae7d6717ebbb05f425d6b2 (diff)
Merge remote branch 'anholt/drm-intel-next' into drm-next-stage
* anholt/drm-intel-next: (103 commits) drm/i915: Use a dmi quirk to skip a broken SDVO TV output. drm/i915: enable/disable LVDS port at DPMS time drm/i915: check for multiple write domains in pin_and_relocate drm/i915: clean-up i915_gem_flush_gpu_write_domain drm/i915: reuse i915_gpu_idle helper drm/i915: ensure lru ordering of fence_list drm/i915: extract fence stealing code drm/i915: fixup active list locking in object_unbind drm/i915: reuse i915_gem_object_put_fence_reg for fence stealing code drm/i915: Add dependency on the intel agp module drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge. drm/i915: Correct the Sandybridge chipset info structs. drm/i915: Disable the hangcheck reset on Sandybridge until we add support. drm/i915: Add a new mobile Sandybridge PCI ID. agp/intel: Add a new Sandybridge HB/IG PCI ID combo. drm/i915, agp/intel: Fix stolen memory size on Sandybridge drm/i915: Correct locking in the modesetting failure path, fixing a BUG_ON. drm/i915: Disable the surface tile swizzling on Sandybridge. agp/intel: Use a non-reserved value for the cache field of the PTEs. drm/i915: Fix sandybridge status page setup. ...
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_drv.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h35
1 files changed, 34 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index c57ad606504..88f4d8669d8 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -295,6 +295,9 @@ typedef struct drm_radeon_private {
int r700_sc_prim_fifo_size;
int r700_sc_hiz_tile_fifo_size;
int r700_sc_earlyz_tile_fifo_fize;
+ int r600_group_size;
+ int r600_npipes;
+ int r600_nbanks;
struct mutex cs_mutex;
u32 cs_id_scnt;
@@ -310,9 +313,11 @@ typedef struct drm_radeon_buf_priv {
u32 age;
} drm_radeon_buf_priv_t;
+struct drm_buffer;
+
typedef struct drm_radeon_kcmd_buffer {
int bufsz;
- char *buf;
+ struct drm_buffer *buffer;
int nbox;
struct drm_clip_rect __user *boxes;
} drm_radeon_kcmd_buffer_t;
@@ -2122,4 +2127,32 @@ extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
write &= mask; \
} while (0)
+/**
+ * Copy given number of dwords from drm buffer to the ring buffer.
+ */
+#define OUT_RING_DRM_BUFFER(buf, sz) do { \
+ int _size = (sz) * 4; \
+ struct drm_buffer *_buf = (buf); \
+ int _part_size; \
+ while (_size > 0) { \
+ _part_size = _size; \
+ \
+ if (write + _part_size/4 > mask) \
+ _part_size = ((mask + 1) - write)*4; \
+ \
+ if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \
+ _part_size = PAGE_SIZE - drm_buffer_index(_buf);\
+ \
+ \
+ \
+ memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \
+ [drm_buffer_index(_buf)], _part_size); \
+ \
+ _size -= _part_size; \
+ write = (write + _part_size/4) & mask; \
+ drm_buffer_advance(_buf, _part_size); \
+ } \
+} while (0)
+
+
#endif /* __RADEON_DRV_H__ */