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authorMichel Dänzer <michel.daenzer@amd.com>2012-03-14 17:12:42 +0100
committerDave Airlie <airlied@redhat.com>2012-03-20 08:47:46 +0000
commit0349af70da5e590793986a0e03dbf2a435f75103 (patch)
treec4104646049fcf3862397cac1b51284bbd48e1b9 /drivers/gpu/drm/radeon/radeon_fb.c
parentc4353016dac10133fa5d8535af83f0c4845a2915 (diff)
drm/radeon: Restrict offset for legacy display engine.
The hardware only takes 27 bits for the offset, so larger offsets are truncated, and the display shows random bits other than the intended ones. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_fb.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 60b97ab1d19..5906914a78b 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -164,7 +164,10 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
ret = radeon_bo_reserve(rbo, false);
if (unlikely(ret != 0))
goto out_unref;
- ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
+ /* Only 27 bit offset for legacy CRTC */
+ ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
+ ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
+ NULL);
if (ret) {
radeon_bo_unreserve(rbo);
goto out_unref;