diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2012-03-20 17:18:15 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2012-03-21 06:55:53 +0000 |
| commit | 498dd8b35ae798c3a6c6c9da029db1806dc2cf93 (patch) | |
| tree | a8ab6d73ee56a12320cf4d2ce5c737e1def029b3 /drivers/gpu/drm/radeon/sid.h | |
| parent | dfcf5f36529d69eb35f4fdedfa6f244c5249698c (diff) | |
drm/radeon/kms: add VM CS checker for SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/sid.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 4d9cdc813d8..ed1b1e5f5dd 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -255,6 +255,8 @@ #define SOFT_RESET_VGT (1 << 14) #define SOFT_RESET_IA (1 << 15) +#define GRBM_GFX_INDEX 0x802C + #define CP_ME_CNTL 0x86D8 #define CP_CE_HALT (1 << 24) #define CP_PFP_HALT (1 << 26) @@ -271,6 +273,8 @@ #define CP_PERFMON_CNTL 0x87FC +#define VGT_VTX_VECT_EJECT_REG 0x88B0 + #define VGT_CACHE_INVALIDATION 0x88C4 #define CACHE_INVALIDATION(x) ((x) << 0) #define VC_ONLY 0 @@ -281,11 +285,23 @@ #define ES_AUTO 1 #define GS_AUTO 2 #define ES_AND_GS_AUTO 3 +#define VGT_ESGS_RING_SIZE 0x88C8 +#define VGT_GSVS_RING_SIZE 0x88CC #define VGT_GS_VERTEX_REUSE 0x88D4 +#define VGT_PRIMITIVE_TYPE 0x8958 +#define VGT_INDEX_TYPE 0x895C + +#define VGT_NUM_INDICES 0x8970 #define VGT_NUM_INSTANCES 0x8974 +#define VGT_TF_RING_SIZE 0x8988 + +#define VGT_HS_OFFCHIP_PARAM 0x89B0 + +#define VGT_TF_MEMORY_BASE 0x89B8 + #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 @@ -293,6 +309,8 @@ #define CLIP_VTX_REORDER_ENA (1 << 0) #define NUM_CLIP_SEQ(x) ((x) << 1) +#define PA_SU_LINE_STIPPLE_VALUE 0x8A60 + #define PA_SC_LINE_STIPPLE_STATE 0x8B10 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 @@ -305,10 +323,21 @@ #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) +#define PA_SC_ENHANCE 0x8BF0 + #define SQ_CONFIG 0x8C00 +#define SQC_CACHES 0x8C08 + #define SX_DEBUG_1 0x9060 +#define SPI_STATIC_THREAD_MGMT_1 0x90E0 +#define SPI_STATIC_THREAD_MGMT_2 0x90E4 +#define SPI_STATIC_THREAD_MGMT_3 0x90E8 +#define SPI_PS_MAX_WAVE_ID 0x90EC + +#define SPI_CONFIG_CNTL 0x9100 + #define SPI_CONFIG_CNTL_1 0x913C #define VTX_DONE_DELAY(x) ((x) << 0) #define INTERP_ONE_PRIM_PER_ROW (1 << 4) @@ -318,6 +347,8 @@ #define TCC_DISABLE_MASK 0xFFFF0000 #define TCC_DISABLE_SHIFT 16 +#define TA_CNTL_AUX 0x9508 + #define CC_RB_BACKEND_DISABLE 0x98F4 #define BACKEND_DISABLE(x) ((x) << 16) #define GB_ADDR_CONFIG 0x98F8 |