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authorMichel Dänzer <daenzer@vmware.com>2010-03-26 19:18:55 +0000
committerDave Airlie <airlied@redhat.com>2010-03-31 13:12:59 +1000
commit3ca82da3ebe019facd611184385897fa614e6b9e (patch)
tree1d7a44ea9adc9d8578ea2e57ea11f459f2d293e4 /drivers/gpu/drm/radeon
parentb8c40d6269d5e515341599b2e395f2dab4490d74 (diff)
drm/radeon/kms: Only restrict BO to visible VRAM size when pinning to VRAM.
This prevented radeon.test=1 from testing transfers from/to GTT beyond the visible VRAM size. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index fc9d00ac6b1..dc7e3f44913 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -185,8 +185,10 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
return 0;
}
radeon_ttm_placement_from_domain(bo, domain);
- /* force to pin into visible video ram */
- bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+ if (domain == RADEON_GEM_DOMAIN_VRAM) {
+ /* force to pin into visible video ram */
+ bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+ }
for (i = 0; i < bo->placement.num_placement; i++)
bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);