diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-02-25 15:18:39 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-27 19:16:30 -0400 |
| commit | 93656cdd3c82a0b9ee1f6755bfdecd30d2541870 (patch) | |
| tree | 42dec1f599c02425b37587c80cfc4bf3883fc647 /drivers/gpu/drm/radeon | |
| parent | beb79f40b8dcc24153678c6ae31faf0fe50b9376 (diff) | |
drm/radeon: add indirect accessors for UVD CTX registers
These are needed for certain UVD power saving features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_reg.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 17 |
2 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h index 58c86cc051b..3ef202629e7 100644 --- a/drivers/gpu/drm/radeon/r600_reg.h +++ b/drivers/gpu/drm/radeon/r600_reg.h @@ -34,6 +34,9 @@ #define R600_RCU_INDEX 0x0100 #define R600_RCU_DATA 0x0104 +#define R600_UVD_CTX_INDEX 0xf4a0 +#define R600_UVD_CTX_DATA 0xf4a4 + #define R600_MC_VM_FB_LOCATION 0x2180 #define R600_MC_FB_BASE_MASK 0x0000FFFF #define R600_MC_FB_BASE_SHIFT 0 diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 706b018e019..4ea447d52b6 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -2094,6 +2094,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) +#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) +#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ @@ -2210,6 +2212,21 @@ static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); } +static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) +{ + u32 r; + + WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); + r = RREG32(R600_UVD_CTX_DATA); + return r; +} + +static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); + WREG32(R600_UVD_CTX_DATA, (v)); +} + void r100_pll_errata_after_index(struct radeon_device *rdev); |