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authorDave Airlie <airlied@gmail.com>2014-08-07 19:53:22 +1000
committerDave Airlie <airlied@gmail.com>2014-08-07 19:53:22 +1000
commitfa1d0ee69ca8c123dd791d52830a2e146985ce85 (patch)
treef8c60a43cd9de72939d8fffe00f64b820ddd0442 /drivers/gpu/drm/tegra/fb.c
parent0c6287ec12fa8f7e295a6ebc5fd331647c5a5469 (diff)
parentef70728c7a6571a1a7115031e932b811f1740b2e (diff)
Merge tag 'drm/tegra/for-3.17-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.17-rc1 Mostly some cleanup all over the place. Pitch alignment limitations of the display controller are now honored and job submission is 64-bit safe. The SOR output (used for eDP) properly configures sync signal polarities according to the display mode rather than hard-coding them to some value and the number of bits per color is now taken from the panel rather than hard-coded to properly support 24-bit vs. 18-bit panels. The DSI controller now properly supports non-continuous clock mode. GEM objects can now have their flags and tiling mode modified via IOCTLs to allow buffers imported from Nouveau to be properly displayed. Newer generations of the Tegra display controller can also detile block linear buffers at scan-out time. Finally the driver now properly exports MODULE_DEVICE_TABLEs to allow it to be automatically loaded when built as a module. * tag 'drm/tegra/for-3.17-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: add MODULE_DEVICE_TABLEs drm/tegra: dc - Reset controller on driver remove drm/tegra: Properly align stride for framebuffers drm/tegra: sor - Configure proper sync polarities drm/tegra: sor - Use bits-per-color from panel drm/tegra: Make job submission 64-bit safe drm/tegra: Allow non-authenticated processes to create buffer objects drm/tegra: Add SET/GET_FLAGS IOCTLs drm/tegra: Add SET/GET_TILING IOCTLs drm/tegra: Implement more tiling modes drm/tegra: dsi - Handle non-continuous clock flag drm/tegra: sor - missing unlock on error
Diffstat (limited to 'drivers/gpu/drm/tegra/fb.c')
-rw-r--r--drivers/gpu/drm/tegra/fb.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index fc1528e0bda..3513d12d5aa 100644
--- a/drivers/gpu/drm/tegra/fb.c
+++ b/drivers/gpu/drm/tegra/fb.c
@@ -46,14 +46,15 @@ bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer)
return false;
}
-bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer)
+int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
+ struct tegra_bo_tiling *tiling)
{
struct tegra_fb *fb = to_tegra_fb(framebuffer);
- if (fb->planes[0]->flags & TEGRA_BO_TILED)
- return true;
+ /* TODO: handle YUV formats? */
+ *tiling = fb->planes[0]->tiling;
- return false;
+ return 0;
}
static void tegra_fb_destroy(struct drm_framebuffer *framebuffer)
@@ -193,6 +194,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
struct tegra_fbdev *fbdev = to_tegra_fbdev(helper);
+ struct tegra_drm *tegra = helper->dev->dev_private;
struct drm_device *drm = helper->dev;
struct drm_mode_fb_cmd2 cmd = { 0 };
unsigned int bytes_per_pixel;
@@ -207,7 +209,8 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper,
cmd.width = sizes->surface_width;
cmd.height = sizes->surface_height;
- cmd.pitches[0] = sizes->surface_width * bytes_per_pixel;
+ cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel,
+ tegra->pitch_align);
cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sizes->surface_depth);