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authorLinus Torvalds <torvalds@linux-foundation.org>2010-06-03 07:19:45 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2010-06-03 07:19:45 -0700
commit1067b6c2bea7fd2cc9da290d865ab3f3b91c8130 (patch)
tree5b20d5fbe9f9a2b3cfbb794018d74606f5031a88 /drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
parenta652883a244901742d6c9733a9eebdf72e3114ea (diff)
parentd8dcaa1dc50f5aecd38d34180cd99d6af8566c88 (diff)
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (41 commits) drm/radeon/kms: make sure display hw is disabled when suspending drm/vmwgfx: Allow userspace to change default layout. Bump minor. drm/vmwgfx: Fix framebuffer modesetting drm/vmwgfx: Fix vga save / restore with display topology. vgaarb: use MIT license vgaarb: convert pr_devel() to pr_debug() drm: fix typos in Linux DRM Developer's Guide drm/radeon/kms/pm: voltage fixes drm/radeon/kms/pm: radeon_set_power_state fixes drm/radeon/kms/pm: patch default power state with default clocks/voltages on r6xx+ drm/radeon/kms/pm: enable SetVoltage on r7xx/evergreen drm/radeon/kms/pm: add support for SetVoltage cmd table (V2) drm/radeon/kms/evergreen: add initial CS parser drm/kms: disable/enable poll around switcheroo on/off drm/nouveau: fixup confusion over which handle the DSM is hanging off. drm/nouveau: attempt to get bios from ACPI v3 drm/nv50: cast IGP memory location to u64 before shifting drm/ttm: Fix ttm_page_alloc.c drm/ttm: Fix cached TTM page allocation. drm/vmwgfx: Remove some leftover debug messages. ...
Diffstat (limited to 'drivers/gpu/drm/vmwgfx/vmwgfx_irq.c')
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_irq.c17
1 files changed, 14 insertions, 3 deletions
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
index 4d7cb539386..e92298a6a38 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
@@ -64,22 +64,33 @@ static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t sequence)
return (busy == 0);
}
+void vmw_update_sequence(struct vmw_private *dev_priv,
+ struct vmw_fifo_state *fifo_state)
+{
+ __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
+
+ uint32_t sequence = ioread32(fifo_mem + SVGA_FIFO_FENCE);
+
+ if (dev_priv->last_read_sequence != sequence) {
+ dev_priv->last_read_sequence = sequence;
+ vmw_fence_pull(&fifo_state->fence_queue, sequence);
+ }
+}
bool vmw_fence_signaled(struct vmw_private *dev_priv,
uint32_t sequence)
{
- __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
struct vmw_fifo_state *fifo_state;
bool ret;
if (likely(dev_priv->last_read_sequence - sequence < VMW_FENCE_WRAP))
return true;
- dev_priv->last_read_sequence = ioread32(fifo_mem + SVGA_FIFO_FENCE);
+ fifo_state = &dev_priv->fifo;
+ vmw_update_sequence(dev_priv, fifo_state);
if (likely(dev_priv->last_read_sequence - sequence < VMW_FENCE_WRAP))
return true;
- fifo_state = &dev_priv->fifo;
if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
vmw_fifo_idle(dev_priv, sequence))
return true;