diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2011-11-02 18:08:25 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-11-03 17:53:26 +0000 |
| commit | 0e2c978ef2248156f36db7fcda8c7b67998ec58a (patch) | |
| tree | 182909abe3a59518140a6f10099a5af0c5c73941 /drivers/gpu/drm | |
| parent | cf2aff6eff251b6fbdaf8c253e65ff7c693de8cd (diff) | |
drm/radeon/kms: don't poll forever if MC GDDR link training fails
Bail if we hit the timeout limit.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 56afaff6299..722cfb39899 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -261,8 +261,11 @@ int ni_mc_load_microcode(struct radeon_device *rdev) WREG32(MC_SEQ_SUP_CNTL, 0x00000001); /* wait for training to complete */ - while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)) - udelay(10); + for (i = 0; i < rdev->usec_timeout; i++) { + if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) + break; + udelay(1); + } if (running) WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); |