diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2014-05-15 22:00:06 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-06-10 16:05:52 +1000 |
| commit | 6e8e268bacb223636f3ade132330b75b70d0f0bf (patch) | |
| tree | 0bf0b8fb4ab048ad109ce7871a1bd8fe3a71b6ae /drivers/gpu/drm | |
| parent | fb7c2a7186b093ed552c0a727cbfe7e156ff7664 (diff) | |
drm/nouveau/disp/dp: support training pattern 3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/dport.c | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/dport.h | 1 |
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c index 46563da2854..13903533d7a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c @@ -202,7 +202,10 @@ dp_link_train_eq(struct dp_state *dp) bool eq_done = false, cr_done = true; int tries = 0, i; - dp_set_training_pattern(dp, 2); + if (dp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED) + dp_set_training_pattern(dp, 3); + else + dp_set_training_pattern(dp, 2); do { if (dp_link_train_update(dp, 400)) @@ -316,8 +319,10 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func, } /* bring capabilities within encoder limits */ + if (nv_oclass(disp)->handle < NV_ENGINE(DISP, 0x90)) + dp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; if ((dp->dpcd[2] & 0x1f) > dp->outp->dpconf.link_nr) { - dp->dpcd[2] &= ~0x1f; + dp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; dp->dpcd[2] |= dp->outp->dpconf.link_nr; } if (dp->dpcd[1] > dp->outp->dpconf.link_bw) diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h b/drivers/gpu/drm/nouveau/core/engine/disp/dport.h index 4d375b759ba..43281c8e9e7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.h @@ -6,6 +6,7 @@ #define DPCD_RC01_MAX_LINK_RATE 0x00001 #define DPCD_RC02 0x00002 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 +#define DPCD_RC02_TPS3_SUPPORTED 0x40 #define DPCD_RC02_MAX_LANE_COUNT 0x1f #define DPCD_RC03 0x00003 #define DPCD_RC03_MAX_DOWNSPREAD 0x01 |