diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2014-10-29 11:03:26 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2014-10-30 15:51:11 +0200 |
| commit | 7809a61176b385ebb3299ea43c58b1bb31ffb8c0 (patch) | |
| tree | 436fce21c4fdab0ff19c7cb6cf30d9957b271d71 /drivers/gpu/drm | |
| parent | b2a9601c587dbc5536546aa54009d1130adedd72 (diff) | |
drm/i915/dp: only use training pattern 3 on platforms that support it
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB
doesn't support DP3 we should even bother trying to use it.
This regression has been introduced in
commit 06ea66b6bb445043dc25a9626254d5c130093199
Author: Todd Previte <tprevite@gmail.com>
Date: Mon Jan 20 10:19:39 2014 -0700
drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable
devices
Reported-by: Dave Airlie <airlied@redhat.com>
Reference: http://mid.gmane.org/1414566170-9868-1-git-send-email-airlied@gmail.com
Cc: Todd Previte <tprevite@gmail.com>
Cc: stable@vger.kernel.org (3.15+)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 464d8ad9bb7..5ad45bfff3f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3731,9 +3731,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) } } - /* Training Pattern 3 support */ + /* Training Pattern 3 support, both source and sink */ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && - intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { + intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED && + (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) { intel_dp->use_tps3 = true; DRM_DEBUG_KMS("Displayport TPS3 supported\n"); } else |