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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-07-13 06:28:22 +0000
committerDave Airlie <airlied@redhat.com>2011-07-25 12:16:25 +0100
commitf6a5693976fbc8e9fe4dde3040820082593c1757 (patch)
treedfbe75b52e4f7c8d5b8d12cd9a6433ea91bfe57f /drivers/gpu
parentdf07d6999e4e502ff474eeafe11ea0055f4cd68d (diff)
drm/radeon: Do an MMIO read on interrupts when not uisng MSIs
When not using MSIs, there is no guarantee that DMA from the device has been fully flushed to point where it's visible to the CPU when taking an interrupt. To get this guarantee, we need to perform an MMIO read from the device, which will flush all outstanding DMAs from bridges between the device and the system. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/r600.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1741af86943..f56e6557983 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3302,6 +3302,10 @@ int r600_irq_process(struct radeon_device *rdev)
if (!rdev->ih.enabled || rdev->shutdown)
return IRQ_NONE;
+ /* No MSIs, need a dummy read to flush PCI DMAs */
+ if (!rdev->msi_enabled)
+ RREG32(IH_RB_WPTR);
+
wptr = r600_get_ih_wptr(rdev);
rptr = rdev->ih.rptr;
DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);