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authorAlex Deucher <alexander.deucher@amd.com>2013-07-11 15:00:14 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-07-14 10:11:24 -0400
commit9847b36af413f32528fc929a0b11d32c2872a05c (patch)
treeac50edfd56284f3412bdfe3583155d450595ec27 /drivers/gpu
parentc2b4cacfe9816c1fe378c785ce8a678cf0635ec6 (diff)
drm/radeon/dpm: disable gfx PG on PALM
Gfx PG doesn't seem to work properly when UVD is initialized on certain PALM boards. Disable gfx PG for now until we sort out a proper fix. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/sumo_dpm.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c
index 11b6b9924f1..ca381028bd7 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -1732,7 +1732,13 @@ int sumo_dpm_init(struct radeon_device *rdev)
pi->enable_sclk_ds = true;
pi->enable_dynamic_m3_arbiter = false;
pi->enable_dynamic_patch_ps = true;
- pi->enable_gfx_power_gating = true;
+ /* Some PALM chips don't seem to properly ungate gfx when UVD is in use;
+ * for now just disable gfx PG.
+ */
+ if (rdev->family == CHIP_PALM)
+ pi->enable_gfx_power_gating = false;
+ else
+ pi->enable_gfx_power_gating = true;
pi->enable_gfx_clock_gating = true;
pi->enable_mg_clock_gating = true;
pi->enable_auto_thermal_throttling = true;