diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2011-05-20 12:36:12 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@gmail.com> | 2011-05-22 20:20:05 +1000 |
| commit | 6f15c506e0cec601fad9fabb7ded0d1811b8002f (patch) | |
| tree | 014495d41f3db1388f08412a4d690267b95bf99e /drivers/gpu | |
| parent | d291767b6056540277497d91baa9120428d7cd1a (diff) | |
drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices
If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters. This should fix DP failures
in the channel equalization loop.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index dab06fb17cb..f5819ba481d 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -815,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, args.v3.ucPostDiv = post_div; args.v3.ucPpll = pll_id; args.v3.ucMiscInfo = (pll_id << 2); + if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) + args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; args.v3.ucTransmitterId = encoder_id; args.v3.ucEncoderMode = encoder_mode; break; |