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authorValentin Longchamp <valentin.longchamp@keymile.com>2014-06-03 11:00:32 +0200
committerWolfram Sang <wsa@the-dreams.de>2014-06-03 14:24:16 +0200
commitd49019a0696b0a234d304a7b3e1e545e850f4691 (patch)
treea9ef8c8a94e6fac4785751d50855b4058b313c8d /drivers/i2c/busses
parent0709dc9711ae6d0559818c31b533a441564dad9b (diff)
i2c: mpc: insert DR read in i2c_fixup()
The mpc_i2c_fixup function is called when the bus is not released by a slave. The function generates 9 pulses that should lead the slave to release the bus. The sequence that generates the pulses disables/enables the I2C module that controls the blocked bus. We have found out on the P2041 SoC that this could cause the CPU to hang (for a short delay). To avoid this, this patch introduces a read to the I2CDR register between the re-enablement of the I2C module in master mode and its returning to the slave mode instead of the delay (the final delay, between the pulses is kept), as proposed in procedure from the P2041 reference manual (16.6.2.3), and the other manuals from the mpc83xx and mpc85xx families. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c/busses')
-rw-r--r--drivers/i2c/busses/i2c-mpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index f5391633b53..6a32aa095f8 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -115,7 +115,7 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c)
for (k = 9; k; k--) {
writeccr(i2c, 0);
writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
- udelay(delay_val);
+ readb(i2c->base + MPC_I2C_DR);
writeccr(i2c, CCR_MEN);
udelay(delay_val << 1);
}