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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-07 19:32:36 -0800
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-07 19:32:36 -0800
commit905adce4094d64a6691df994e424fbf486301adc (patch)
treec4e3a2fb1465eeb713b3bec5ef4634c28179a14b /drivers/ide/pci/piix.c
parent78149df6d565c36675463352d0bfe0000b02b7a7 (diff)
parent1e8f34f7d88c969a06229a786241839d49dd63e3 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6: (23 commits) ide-acpi support warning fix ACPI support for IDE devices IDE Driver for Delkin/Lexar/etc.. cardbus CF adapter ide: it8213 IDE driver update (version 2) ide: add it8213 IDE driver tc86c001: add missing __init tag for tc86c001_ide_init() tc86c001: mark init_chipset_tc86c001() with __devinit tag tc86c001: init_hwif_tc86c001() can be static ide: add Toshiba TC86C001 IDE driver (take 2) pdc202xx_new: remove check_in_drive_lists abomination pdc202xx_new: remove useless code slc90e66: carry over fixes from piix driver piix: tuneproc() fixes/cleanups piix: fix 82371MX enablebits hpt366: HPT36x PCI clock detection fix hpt366: init code rewrite hpt366: clean up DMA timeout handling for HPT370 hpt366: merge HPT37x speedproc handlers hpt366: cache channel's MCR address hpt366: switch to using pci_get_slot ...
Diffstat (limited to 'drivers/ide/pci/piix.c')
-rw-r--r--drivers/ide/pci/piix.c31
1 files changed, 18 insertions, 13 deletions
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
index edb37f3d558..52cfc2ac22c 100644
--- a/drivers/ide/pci/piix.c
+++ b/drivers/ide/pci/piix.c
@@ -1,5 +1,5 @@
/*
- * linux/drivers/ide/pci/piix.c Version 0.45 May 12, 2006
+ * linux/drivers/ide/pci/piix.c Version 0.46 December 3, 2006
*
* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
@@ -163,7 +163,7 @@ static u8 piix_ratemask (ide_drive_t *drive)
* if the drive cannot see an 80pin cable.
*/
if (!eighty_ninty_three(drive))
- mode = min(mode, (u8)1);
+ mode = min_t(u8, mode, 1);
return mode;
}
@@ -216,7 +216,7 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
{
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
- int is_slave = (&hwif->drives[1] == drive);
+ int is_slave = drive->dn & 1;
int master_port = hwif->channel ? 0x42 : 0x40;
int slave_port = 0x44;
unsigned long flags;
@@ -225,7 +225,7 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
static DEFINE_SPINLOCK(tune_lock);
int control = 0;
- /* ISP RTC */
+ /* ISP RTC */
static const u8 timings[][2]= {
{ 0, 0 },
{ 0, 0 },
@@ -233,7 +233,7 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
{ 2, 1 },
{ 2, 3 }, };
- pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
+ pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
/*
* Master vs slave is synchronized above us but the slave register is
@@ -243,25 +243,24 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
spin_lock_irqsave(&tune_lock, flags);
pci_read_config_word(dev, master_port, &master_data);
- if (pio >= 2)
+ if (pio > 1)
control |= 1; /* Programmable timing on */
if (drive->media == ide_disk)
control |= 4; /* Prefetch, post write */
- if (pio >= 3)
+ if (pio > 2)
control |= 2; /* IORDY */
if (is_slave) {
- master_data = master_data | 0x4000;
+ master_data |= 0x4000;
+ master_data &= ~0x0070;
if (pio > 1) {
/* enable PPE, IE and TIME */
master_data = master_data | (control << 4);
- } else {
- master_data &= ~0x0070;
}
pci_read_config_byte(dev, slave_port, &slave_data);
slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
} else {
- master_data = master_data & 0xccf8;
+ master_data &= ~0x3307;
if (pio > 1) {
/* enable PPE, IE and TIME */
master_data = master_data | control;
@@ -539,13 +538,19 @@ static ide_pci_device_t piix_pci_info[] __devinitdata = {
/* 0 */ DECLARE_PIIX_DEV("PIIXa"),
/* 1 */ DECLARE_PIIX_DEV("PIIXb"),
- { /* 2 */
+ /* 2 */
+ { /*
+ * MPIIX actually has only a single IDE channel mapped to
+ * the primary or secondary ports depending on the value
+ * of the bit 14 of the IDETIM register at offset 0x6c
+ */
.name = "MPIIX",
.init_hwif = init_hwif_piix,
.channels = 2,
.autodma = NODMA,
- .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}},
+ .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
.bootable = ON_BOARD,
+ .flags = IDEPCI_FLAG_ISA_PORTS
},
/* 3 */ DECLARE_PIIX_DEV("PIIX3"),