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authorSteve Wise <swise@opengridcomputing.com>2010-09-17 15:40:15 -0500
committerRoland Dreier <rolandd@cisco.com>2010-09-28 10:53:50 -0700
commit40dbf6ee381008e471d3c4a332971247b7799744 (patch)
tree6249fb3fd9cca9e2e42c01a798ef21b4f5a1e328 /drivers/idle
parent410ade4c26bdf256fea3246e968a12409eb08763 (diff)
RDMA/cxgb4: Fastreg NSMR fixes
- Remove dsgl support - doesn't work in T4. - Wrap the immediate PBL as needed when building it in the wr. - Adjust max pbl depth allowed based on ulptx alignment requirements. - Bump the slots per SQ to 5 to allow up to 128MB fast registers. - Advertise fastreg support by default. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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