[media] mt2063: Fix some Coding styles at mt2063.h

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

1 files changed, 119 insertions, 152 deletions

diff --git a/drivers/media/common/tuners/mt2063.h b/drivers/media/common/tuners/mt2063.h
index 4912f8902aa..8fa4411d30d 100644
--- a/drivers/media/common/tuners/mt2063.h
+++ b/drivers/media/common/tuners/mt2063.h
@@ -4,19 +4,6 @@
 #include <linux/dvb/frontend.h>
 #include "dvb_frontend.h"
 
-//context of mt2063_errordef.h  <Henry> ======================================
-//#################################################################
-//=================================================================
-
-/*
-** Note to users:  DO NOT EDIT THIS FILE
-**
-** If you wish to rename any of the "user defined" bits,
-** it should be done in the user file that includes this
-** source file (e.g. mt_userdef.h)
-**
-*/
-
 #define MT2063_ERROR (1 << 31)
 #define MT2063_USER_ERROR (1 << 30)
 
@@ -88,37 +75,28 @@
 /*  Info: Downconverter frequency is out of range (may be reason for MT_DPC_UNLOCK) */
 #define MT2063_DNC_RANGE                    (0x08000000)
 
-//end of mt2063_errordef.h
-//=================================================================
-//#################################################################
-//=================================================================
-
-//context of mt2063_userdef.h   <Henry> ======================================
-//#################################################################
-//=================================================================
 /*
-**  Data Types
-*/
+ *  Data Types
+ */
 #define MT2060_CNT 10
 
 typedef unsigned char U8Data;	/*  type corresponds to 8 bits      */
 typedef unsigned int UData_t;	/*  type must be at least 32 bits   */
 typedef int SData_t;		/*  type must be at least 32 bits   */
 typedef void *Handle_t;		/*  memory pointer type             */
-//typedef double          FData_t;        /*  floating point data type        */
 
 #define MAX_UDATA         (4294967295)	/*  max value storable in UData_t   */
 
 /*
-** Define an MTxxxx_CNT macro for each type of tuner that will be built
-** into your application (e.g., MT2121, MT2060). MT_TUNER_CNT
-** must be set to the SUM of all of the MTxxxx_CNT macros.
-**
-** #define MT2050_CNT  (1)
-** #define MT2060_CNT  (1)
-** #define MT2111_CNT  (1)
-** #define MT2121_CNT  (3)
-*/
+ * Define an MTxxxx_CNT macro for each type of tuner that will be built
+ * into your application (e.g., MT2121, MT2060). MT_TUNER_CNT
+ * must be set to the SUM of all of the MTxxxx_CNT macros.
+ *
+ * #define MT2050_CNT  (1)
+ * #define MT2060_CNT  (1)
+ * #define MT2111_CNT  (1)
+ * #define MT2121_CNT  (3)
+ */
 
 #define MT2063_CNT (1)
 
@@ -142,22 +120,15 @@ void MT2063_Sleep(Handle_t hUserData, UData_t nMinDelayTime);
 UData_t MT2060_TunerGain(Handle_t hUserData, SData_t * pMeas);
 #endif
 #endif
-//end of mt2063_userdef.h
-//=================================================================
-//#################################################################
-//=================================================================
-
-//context of mt2063_spruavoid.h <Henry> ======================================
-//#################################################################
-//=================================================================
+
 /*
-**  Constant defining the version of the following structure
-**  and therefore the API for this code.
-**
-**  When compiling the tuner driver, the preprocessor will
-**  check against this version number to make sure that
-**  it matches the version that the tuner driver knows about.
-*/
+ *  Constant defining the version of the following structure
+ *  and therefore the API for this code.
+ *
+ *  When compiling the tuner driver, the preprocessor will
+ *  check against this version number to make sure that
+ *  it matches the version that the tuner driver knows about.
+ */
 /* Version 010201 => 1.21 */
 #define MT2063_AVOID_SPURS_INFO_VERSION 010201
 
@@ -171,10 +142,10 @@ UData_t MT2060_TunerGain(Handle_t hUserData, SData_t * pMeas);
 #define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
 
 enum MT2063_DECT_Avoid_Type {
-	MT2063_NO_DECT_AVOIDANCE = 0,	/* Do not create DECT exclusion zones.     */
+	MT2063_NO_DECT_AVOIDANCE = 0,				/* Do not create DECT exclusion zones.     */
 	MT2063_AVOID_US_DECT = MT2063_DECT_AVOID_US_FREQS,	/* Avoid US DECT frequencies.              */
 	MT2063_AVOID_EURO_DECT = MT2063_DECT_AVOID_EURO_FREQS,	/* Avoid European DECT frequencies.        */
-	MT2063_AVOID_BOTH	/* Avoid both regions. Not typically used. */
+	MT2063_AVOID_BOTH					/* Avoid both regions. Not typically used. */
 };
 
 #define MT2063_MAX_ZONES 48
@@ -188,8 +159,8 @@ struct MT2063_ExclZone_t {
 };
 
 /*
-**  Structure of data needed for Spur Avoidance
-*/
+ *  Structure of data needed for Spur Avoidance
+ */
 struct MT2063_AvoidSpursData_t {
 	UData_t nAS_Algorithm;
 	UData_t f_ref;
@@ -234,15 +205,11 @@ UData_t MT2063_AvoidSpurs(Handle_t h, struct MT2063_AvoidSpursData_t *pAS_Info);
 
 UData_t MT2063_AvoidSpursVersion(void);
 
-//end of mt2063_spuravoid.h
-//=================================================================
-//#################################################################
-//=================================================================
 
 /*
-**  Values returned by the MT2063's on-chip temperature sensor
-**  to be read/written.
-*/
+ *  Values returned by the MT2063's on-chip temperature sensor
+ *  to be read/written.
+ */
 enum MT2063_Temperature {
 	MT2063_T_0C = 0,	/*  Temperature approx 0C           */
 	MT2063_T_10C,		/*  Temperature approx 10C          */
@@ -263,8 +230,8 @@ enum MT2063_Temperature {
 };
 
 /*
-** Parameters for selecting GPIO bits
-*/
+ * Parameters for selecting GPIO bits
+ */
 enum MT2063_GPIO_Attr {
 	MT2063_GPIO_IN,
 	MT2063_GPIO_DIR,
@@ -278,11 +245,11 @@ enum MT2063_GPIO_ID {
 };
 
 /*
-**  Parameter for function MT2063_SetExtSRO that specifies the external
-**  SRO drive frequency.
-**
-**  MT2063_EXT_SRO_OFF is the power-up default value.
-*/
+ *  Parameter for function MT2063_SetExtSRO that specifies the external
+ *  SRO drive frequency.
+ *
+ *  MT2063_EXT_SRO_OFF is the power-up default value.
+ */
 enum MT2063_Ext_SRO {
 	MT2063_EXT_SRO_OFF,	/*  External SRO drive off          */
 	MT2063_EXT_SRO_BY_4,	/*  External SRO drive divide by 4  */
@@ -291,31 +258,31 @@ enum MT2063_Ext_SRO {
 };
 
 /*
-**  Parameter for function MT2063_SetPowerMask that specifies the power down
-**  of various sections of the MT2063.
-*/
+ *  Parameter for function MT2063_SetPowerMask that specifies the power down
+ *  of various sections of the MT2063.
+ */
 enum MT2063_Mask_Bits {
-	MT2063_REG_SD = 0x0040,	/* Shutdown regulator                 */
-	MT2063_SRO_SD = 0x0020,	/* Shutdown SRO                       */
-	MT2063_AFC_SD = 0x0010,	/* Shutdown AFC A/D                   */
-	MT2063_PD_SD = 0x0002,	/* Enable power detector shutdown     */
+	MT2063_REG_SD = 0x0040,		/* Shutdown regulator                 */
+	MT2063_SRO_SD = 0x0020,		/* Shutdown SRO                       */
+	MT2063_AFC_SD = 0x0010,		/* Shutdown AFC A/D                   */
+	MT2063_PD_SD = 0x0002,		/* Enable power detector shutdown     */
 	MT2063_PDADC_SD = 0x0001,	/* Enable power detector A/D shutdown */
-	MT2063_VCO_SD = 0x8000,	/* Enable VCO shutdown                */
-	MT2063_LTX_SD = 0x4000,	/* Enable LTX shutdown                */
-	MT2063_LT1_SD = 0x2000,	/* Enable LT1 shutdown                */
-	MT2063_LNA_SD = 0x1000,	/* Enable LNA shutdown                */
-	MT2063_UPC_SD = 0x0800,	/* Enable upconverter shutdown        */
-	MT2063_DNC_SD = 0x0400,	/* Enable downconverter shutdown      */
-	MT2063_VGA_SD = 0x0200,	/* Enable VGA shutdown                */
-	MT2063_AMP_SD = 0x0100,	/* Enable AMP shutdown                */
-	MT2063_ALL_SD = 0xFF73,	/* All shutdown bits for this tuner   */
-	MT2063_NONE_SD = 0x0000	/* No shutdown bits                   */
+	MT2063_VCO_SD = 0x8000,		/* Enable VCO shutdown                */
+	MT2063_LTX_SD = 0x4000,		/* Enable LTX shutdown                */
+	MT2063_LT1_SD = 0x2000,		/* Enable LT1 shutdown                */
+	MT2063_LNA_SD = 0x1000,		/* Enable LNA shutdown                */
+	MT2063_UPC_SD = 0x0800,		/* Enable upconverter shutdown        */
+	MT2063_DNC_SD = 0x0400,		/* Enable downconverter shutdown      */
+	MT2063_VGA_SD = 0x0200,		/* Enable VGA shutdown                */
+	MT2063_AMP_SD = 0x0100,		/* Enable AMP shutdown                */
+	MT2063_ALL_SD = 0xFF73,		/* All shutdown bits for this tuner   */
+	MT2063_NONE_SD = 0x0000		/* No shutdown bits                   */
 };
 
 /*
-**  Parameter for function MT2063_GetParam & MT2063_SetParam that
-**  specifies the tuning algorithm parameter to be read/written.
-*/
+ *  Parameter for function MT2063_GetParam & MT2063_SetParam that
+ *  specifies the tuning algorithm parameter to be read/written.
+ */
 enum MT2063_Param {
 	/*  tuner address                                  set by MT2063_Open() */
 	MT2063_IC_ADDR,
@@ -462,8 +429,8 @@ enum MT2063_Param {
 };
 
 /*
-**  Parameter for selecting tuner mode
-*/
+ *  Parameter for selecting tuner mode
+ */
 enum MT2063_RCVR_MODES {
 	MT2063_CABLE_QAM = 0,	/* Digital cable              */
 	MT2063_CABLE_ANALOG,	/* Analog cable               */
@@ -475,8 +442,8 @@ enum MT2063_RCVR_MODES {
 };
 
 /*
-**  Possible values for MT2063_DNC_OUTPUT
-*/
+ *  Possible values for MT2063_DNC_OUTPUT
+ */
 enum MT2063_DNC_Output_Enable {
 	MT2063_DNC_NONE = 0,
 	MT2063_DNC_1,
@@ -490,66 +457,66 @@ enum MT2063_DNC_Output_Enable {
 */
 enum MT2063_Register_Offsets {
 	MT2063_REG_PART_REV = 0,	/*  0x00: Part/Rev Code         */
-	MT2063_REG_LO1CQ_1,	/*  0x01: LO1C Queued Byte 1    */
-	MT2063_REG_LO1CQ_2,	/*  0x02: LO1C Queued Byte 2    */
-	MT2063_REG_LO2CQ_1,	/*  0x03: LO2C Queued Byte 1    */
-	MT2063_REG_LO2CQ_2,	/*  0x04: LO2C Queued Byte 2    */
-	MT2063_REG_LO2CQ_3,	/*  0x05: LO2C Queued Byte 3    */
-	MT2063_REG_RSVD_06,	/*  0x06: Reserved              */
-	MT2063_REG_LO_STATUS,	/*  0x07: LO Status             */
-	MT2063_REG_FIFFC,	/*  0x08: FIFF Center           */
-	MT2063_REG_CLEARTUNE,	/*  0x09: ClearTune Filter      */
-	MT2063_REG_ADC_OUT,	/*  0x0A: ADC_OUT               */
-	MT2063_REG_LO1C_1,	/*  0x0B: LO1C Byte 1           */
-	MT2063_REG_LO1C_2,	/*  0x0C: LO1C Byte 2           */
-	MT2063_REG_LO2C_1,	/*  0x0D: LO2C Byte 1           */
-	MT2063_REG_LO2C_2,	/*  0x0E: LO2C Byte 2           */
-	MT2063_REG_LO2C_3,	/*  0x0F: LO2C Byte 3           */
-	MT2063_REG_RSVD_10,	/*  0x10: Reserved              */
-	MT2063_REG_PWR_1,	/*  0x11: PWR Byte 1            */
-	MT2063_REG_PWR_2,	/*  0x12: PWR Byte 2            */
-	MT2063_REG_TEMP_STATUS,	/*  0x13: Temp Status           */
-	MT2063_REG_XO_STATUS,	/*  0x14: Crystal Status        */
-	MT2063_REG_RF_STATUS,	/*  0x15: RF Attn Status        */
-	MT2063_REG_FIF_STATUS,	/*  0x16: FIF Attn Status       */
-	MT2063_REG_LNA_OV,	/*  0x17: LNA Attn Override     */
-	MT2063_REG_RF_OV,	/*  0x18: RF Attn Override      */
-	MT2063_REG_FIF_OV,	/*  0x19: FIF Attn Override     */
-	MT2063_REG_LNA_TGT,	/*  0x1A: Reserved              */
-	MT2063_REG_PD1_TGT,	/*  0x1B: Pwr Det 1 Target      */
-	MT2063_REG_PD2_TGT,	/*  0x1C: Pwr Det 2 Target      */
-	MT2063_REG_RSVD_1D,	/*  0x1D: Reserved              */
-	MT2063_REG_RSVD_1E,	/*  0x1E: Reserved              */
-	MT2063_REG_RSVD_1F,	/*  0x1F: Reserved              */
-	MT2063_REG_RSVD_20,	/*  0x20: Reserved              */
-	MT2063_REG_BYP_CTRL,	/*  0x21: Bypass Control        */
-	MT2063_REG_RSVD_22,	/*  0x22: Reserved              */
-	MT2063_REG_RSVD_23,	/*  0x23: Reserved              */
-	MT2063_REG_RSVD_24,	/*  0x24: Reserved              */
-	MT2063_REG_RSVD_25,	/*  0x25: Reserved              */
-	MT2063_REG_RSVD_26,	/*  0x26: Reserved              */
-	MT2063_REG_RSVD_27,	/*  0x27: Reserved              */
-	MT2063_REG_FIFF_CTRL,	/*  0x28: FIFF Control          */
-	MT2063_REG_FIFF_OFFSET,	/*  0x29: FIFF Offset           */
-	MT2063_REG_CTUNE_CTRL,	/*  0x2A: Reserved              */
-	MT2063_REG_CTUNE_OV,	/*  0x2B: Reserved              */
-	MT2063_REG_CTRL_2C,	/*  0x2C: Reserved              */
-	MT2063_REG_FIFF_CTRL2,	/*  0x2D: Fiff Control          */
-	MT2063_REG_RSVD_2E,	/*  0x2E: Reserved              */
-	MT2063_REG_DNC_GAIN,	/*  0x2F: DNC Control           */
-	MT2063_REG_VGA_GAIN,	/*  0x30: VGA Gain Ctrl         */
-	MT2063_REG_RSVD_31,	/*  0x31: Reserved              */
-	MT2063_REG_TEMP_SEL,	/*  0x32: Temperature Selection */
-	MT2063_REG_RSVD_33,	/*  0x33: Reserved              */
-	MT2063_REG_RSVD_34,	/*  0x34: Reserved              */
-	MT2063_REG_RSVD_35,	/*  0x35: Reserved              */
-	MT2063_REG_RSVD_36,	/*  0x36: Reserved              */
-	MT2063_REG_RSVD_37,	/*  0x37: Reserved              */
-	MT2063_REG_RSVD_38,	/*  0x38: Reserved              */
-	MT2063_REG_RSVD_39,	/*  0x39: Reserved              */
-	MT2063_REG_RSVD_3A,	/*  0x3A: Reserved              */
-	MT2063_REG_RSVD_3B,	/*  0x3B: Reserved              */
-	MT2063_REG_RSVD_3C,	/*  0x3C: Reserved              */
+	MT2063_REG_LO1CQ_1,		/*  0x01: LO1C Queued Byte 1    */
+	MT2063_REG_LO1CQ_2,		/*  0x02: LO1C Queued Byte 2    */
+	MT2063_REG_LO2CQ_1,		/*  0x03: LO2C Queued Byte 1    */
+	MT2063_REG_LO2CQ_2,		/*  0x04: LO2C Queued Byte 2    */
+	MT2063_REG_LO2CQ_3,		/*  0x05: LO2C Queued Byte 3    */
+	MT2063_REG_RSVD_06,		/*  0x06: Reserved              */
+	MT2063_REG_LO_STATUS,		/*  0x07: LO Status             */
+	MT2063_REG_FIFFC,		/*  0x08: FIFF Center           */
+	MT2063_REG_CLEARTUNE,		/*  0x09: ClearTune Filter      */
+	MT2063_REG_ADC_OUT,		/*  0x0A: ADC_OUT               */
+	MT2063_REG_LO1C_1,		/*  0x0B: LO1C Byte 1           */
+	MT2063_REG_LO1C_2,		/*  0x0C: LO1C Byte 2           */
+	MT2063_REG_LO2C_1,		/*  0x0D: LO2C Byte 1           */
+	MT2063_REG_LO2C_2,		/*  0x0E: LO2C Byte 2           */
+	MT2063_REG_LO2C_3,		/*  0x0F: LO2C Byte 3           */
+	MT2063_REG_RSVD_10,		/*  0x10: Reserved              */
+	MT2063_REG_PWR_1,		/*  0x11: PWR Byte 1            */
+	MT2063_REG_PWR_2,		/*  0x12: PWR Byte 2            */
+	MT2063_REG_TEMP_STATUS,		/*  0x13: Temp Status           */
+	MT2063_REG_XO_STATUS,		/*  0x14: Crystal Status        */
+	MT2063_REG_RF_STATUS,		/*  0x15: RF Attn Status        */
+	MT2063_REG_FIF_STATUS,		/*  0x16: FIF Attn Status       */
+	MT2063_REG_LNA_OV,		/*  0x17: LNA Attn Override     */
+	MT2063_REG_RF_OV,		/*  0x18: RF Attn Override      */
+	MT2063_REG_FIF_OV,		/*  0x19: FIF Attn Override     */
+	MT2063_REG_LNA_TGT,		/*  0x1A: Reserved              */
+	MT2063_REG_PD1_TGT,		/*  0x1B: Pwr Det 1 Target      */
+	MT2063_REG_PD2_TGT,		/*  0x1C: Pwr Det 2 Target      */
+	MT2063_REG_RSVD_1D,		/*  0x1D: Reserved              */
+	MT2063_REG_RSVD_1E,		/*  0x1E: Reserved              */
+	MT2063_REG_RSVD_1F,		/*  0x1F: Reserved              */
+	MT2063_REG_RSVD_20,		/*  0x20: Reserved              */
+	MT2063_REG_BYP_CTRL,		/*  0x21: Bypass Control        */
+	MT2063_REG_RSVD_22,		/*  0x22: Reserved              */
+	MT2063_REG_RSVD_23,		/*  0x23: Reserved              */
+	MT2063_REG_RSVD_24,		/*  0x24: Reserved              */
+	MT2063_REG_RSVD_25,		/*  0x25: Reserved              */
+	MT2063_REG_RSVD_26,		/*  0x26: Reserved              */
+	MT2063_REG_RSVD_27,		/*  0x27: Reserved              */
+	MT2063_REG_FIFF_CTRL,		/*  0x28: FIFF Control          */
+	MT2063_REG_FIFF_OFFSET,		/*  0x29: FIFF Offset           */
+	MT2063_REG_CTUNE_CTRL,		/*  0x2A: Reserved              */
+	MT2063_REG_CTUNE_OV,		/*  0x2B: Reserved              */
+	MT2063_REG_CTRL_2C,		/*  0x2C: Reserved              */
+	MT2063_REG_FIFF_CTRL2,		/*  0x2D: Fiff Control          */
+	MT2063_REG_RSVD_2E,		/*  0x2E: Reserved              */
+	MT2063_REG_DNC_GAIN,		/*  0x2F: DNC Control           */
+	MT2063_REG_VGA_GAIN,		/*  0x30: VGA Gain Ctrl         */
+	MT2063_REG_RSVD_31,		/*  0x31: Reserved              */
+	MT2063_REG_TEMP_SEL,		/*  0x32: Temperature Selection */
+	MT2063_REG_RSVD_33,		/*  0x33: Reserved              */
+	MT2063_REG_RSVD_34,		/*  0x34: Reserved              */
+	MT2063_REG_RSVD_35,		/*  0x35: Reserved              */
+	MT2063_REG_RSVD_36,		/*  0x36: Reserved              */
+	MT2063_REG_RSVD_37,		/*  0x37: Reserved              */
+	MT2063_REG_RSVD_38,		/*  0x38: Reserved              */
+	MT2063_REG_RSVD_39,		/*  0x39: Reserved              */
+	MT2063_REG_RSVD_3A,		/*  0x3A: Reserved              */
+	MT2063_REG_RSVD_3B,		/*  0x3B: Reserved              */
+	MT2063_REG_RSVD_3C,		/*  0x3C: Reserved              */
 	MT2063_REG_END_REGS
 };
 
@@ -667,6 +634,6 @@ static inline struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
 	return NULL;
 }
 
-#endif //CONFIG_DVB_MT2063
+#endif /* CONFIG_DVB_MT2063 */
 
-#endif //__MT2063_H__
+#endif /* __MT2063_H__ */