diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-05 13:10:00 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-05 13:10:00 -0700 |
| commit | 463b21fb27509061b3e97fb4fa69f26d089ddaf4 (patch) | |
| tree | 4d8fb4302e4edbfb5c4dfe7c6570a4c1b4c07756 /drivers/media/platform/s5p-jpeg/jpeg-regs.h | |
| parent | 8e0c0832348c7fda1c85d67697cfe4adf077344c (diff) | |
| parent | 97e9858ed5525af5355769cd98b25b5ec94c0c85 (diff) | |
Merge branch 'topic/exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull exynos media updates from Mauro Carvalho Chehab:
"These are the remaining patches I have for the merge windows. It
basically adds a new sensor and adds the needed DT bits for it to
work"
* 'topic/exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media:
[media] s5p-fimc: Remove reference to outdated macro
[media] s5p-jpeg: Fix broken indentation in jpeg-regs.h
[media] exynos4-is: Add the FIMC-IS ISP capture DMA driver
[media] exynos4-is: Add support for asynchronous subdevices registration
[media] exynos4-is: Add clock provider for the SCLK_CAM clock outputs
[media] exynos4-is: Use external s5k6a3 sensor driver
[media] V4L: s5c73m3: Add device tree support
[media] V4L: Add driver for s5k6a3 image sensor
[media] Documentation: devicetree: Update Samsung FIMC DT binding
[media] Documentation: dt: Add binding documentation for S5C73M3 camera
[media] Documentation: dt: Add binding documentation for S5K6A3 image sensor
Diffstat (limited to 'drivers/media/platform/s5p-jpeg/jpeg-regs.h')
| -rw-r--r-- | drivers/media/platform/s5p-jpeg/jpeg-regs.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-regs.h b/drivers/media/platform/s5p-jpeg/jpeg-regs.h index 33f2c7374cf..57fb05bb8c7 100644 --- a/drivers/media/platform/s5p-jpeg/jpeg-regs.h +++ b/drivers/media/platform/s5p-jpeg/jpeg-regs.h @@ -210,19 +210,19 @@ /* JPEG CNTL Register bit */ #define EXYNOS4_ENC_DEC_MODE_MASK (0xfffffffc << 0) -#define EXYNOS4_DEC_MODE (1 << 0) -#define EXYNOS4_ENC_MODE (1 << 1) +#define EXYNOS4_DEC_MODE (1 << 0) +#define EXYNOS4_ENC_MODE (1 << 1) #define EXYNOS4_AUTO_RST_MARKER (1 << 2) #define EXYNOS4_RST_INTERVAL_SHIFT 3 #define EXYNOS4_RST_INTERVAL(x) (((x) & 0xffff) \ << EXYNOS4_RST_INTERVAL_SHIFT) #define EXYNOS4_HUF_TBL_EN (1 << 19) #define EXYNOS4_HOR_SCALING_SHIFT 20 -#define EXYNOS4_HOR_SCALING_MASK (3 << EXYNOS4_HOR_SCALING_SHIFT) +#define EXYNOS4_HOR_SCALING_MASK (3 << EXYNOS4_HOR_SCALING_SHIFT) #define EXYNOS4_HOR_SCALING(x) (((x) & 0x3) \ << EXYNOS4_HOR_SCALING_SHIFT) #define EXYNOS4_VER_SCALING_SHIFT 22 -#define EXYNOS4_VER_SCALING_MASK (3 << EXYNOS4_VER_SCALING_SHIFT) +#define EXYNOS4_VER_SCALING_MASK (3 << EXYNOS4_VER_SCALING_SHIFT) #define EXYNOS4_VER_SCALING(x) (((x) & 0x3) \ << EXYNOS4_VER_SCALING_SHIFT) #define EXYNOS4_PADDING (1 << 27) @@ -238,8 +238,8 @@ #define EXYNOS4_FRAME_ERR_EN (1 << 4) #define EXYNOS4_INT_EN_ALL (0x1f << 0) -#define EXYNOS4_MOD_REG_PROC_ENC (0 << 3) -#define EXYNOS4_MOD_REG_PROC_DEC (1 << 3) +#define EXYNOS4_MOD_REG_PROC_ENC (0 << 3) +#define EXYNOS4_MOD_REG_PROC_DEC (1 << 3) #define EXYNOS4_MOD_REG_SUBSAMPLE_444 (0 << 0) #define EXYNOS4_MOD_REG_SUBSAMPLE_422 (1 << 0) @@ -270,7 +270,7 @@ #define EXYNOS4_DEC_YUV_420_IMG (4 << 0) #define EXYNOS4_GRAY_IMG_IP_SHIFT 3 -#define EXYNOS4_GRAY_IMG_IP_MASK (7 << EXYNOS4_GRAY_IMG_IP_SHIFT) +#define EXYNOS4_GRAY_IMG_IP_MASK (7 << EXYNOS4_GRAY_IMG_IP_SHIFT) #define EXYNOS4_GRAY_IMG_IP (4 << EXYNOS4_GRAY_IMG_IP_SHIFT) #define EXYNOS4_RGB_IP_SHIFT 6 @@ -278,18 +278,18 @@ #define EXYNOS4_RGB_IP_RGB_16BIT_IMG (4 << EXYNOS4_RGB_IP_SHIFT) #define EXYNOS4_RGB_IP_RGB_32BIT_IMG (5 << EXYNOS4_RGB_IP_SHIFT) -#define EXYNOS4_YUV_444_IP_SHIFT 9 +#define EXYNOS4_YUV_444_IP_SHIFT 9 #define EXYNOS4_YUV_444_IP_MASK (7 << EXYNOS4_YUV_444_IP_SHIFT) #define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG (4 << EXYNOS4_YUV_444_IP_SHIFT) #define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG (5 << EXYNOS4_YUV_444_IP_SHIFT) -#define EXYNOS4_YUV_422_IP_SHIFT 12 +#define EXYNOS4_YUV_422_IP_SHIFT 12 #define EXYNOS4_YUV_422_IP_MASK (7 << EXYNOS4_YUV_422_IP_SHIFT) #define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG (4 << EXYNOS4_YUV_422_IP_SHIFT) #define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG (5 << EXYNOS4_YUV_422_IP_SHIFT) #define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG (6 << EXYNOS4_YUV_422_IP_SHIFT) -#define EXYNOS4_YUV_420_IP_SHIFT 15 +#define EXYNOS4_YUV_420_IP_SHIFT 15 #define EXYNOS4_YUV_420_IP_MASK (7 << EXYNOS4_YUV_420_IP_SHIFT) #define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG (4 << EXYNOS4_YUV_420_IP_SHIFT) #define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG (5 << EXYNOS4_YUV_420_IP_SHIFT) @@ -303,8 +303,8 @@ #define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK 0x03 -#define EXYNOS4_SWAP_CHROMA_CRCB (1 << 26) -#define EXYNOS4_SWAP_CHROMA_CBCR (0 << 26) +#define EXYNOS4_SWAP_CHROMA_CRCB (1 << 26) +#define EXYNOS4_SWAP_CHROMA_CBCR (0 << 26) /* JPEG HUFF count Register bit */ #define EXYNOS4_HUFF_COUNT_MASK 0xffff |