diff options
| author | Trent Piepho <xyzzy@speakeasy.org> | 2007-08-18 22:09:42 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@infradead.org> | 2007-10-09 22:05:55 -0300 |
| commit | 59fd8f8d8ee9f7539758419965381bcccfa6f798 (patch) | |
| tree | 314a527b8adea2dc3460d933322832de9a58269d /drivers/media/video/cx88/cx88-reg.h | |
| parent | 5ba862b77e2d7f9e6e2cb133c43be32ac612aea5 (diff) | |
V4L/DVB (6066): cx88-alsa: Change order of interrupt enabling, fix spurious IRQs
Currently the driver turns on audio interrupts, then sets the audio interrupt
mask to select which interrupts to get. One could received unwanted
interrupts since the mask is set _after_ interrupts have already been turned
on. Change the order of the operations, and clear any audio interrupt status
bits that are already set for good measure.
Before changing the SRAM FIFO parameters, make sure the FIFO isn't being used.
This shouldn't happen with just the ALSA driver, as it should never try to
turn on FIFO/RISC/DMA while they are already on. However, the V4L driver
needs to turn the audio FIFO on for analog audio output to work (undocumented
cx88 bug). The FIFO parameters are in an inconsistent state while they are
updated, and this results in many FIFO sync error IRQs if the FIFO is in use
while it's in this inconsistent state.
Also create and use a bunch of symbolic constants for audio interrupt mask
bits.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/video/cx88/cx88-reg.h')
| -rw-r--r-- | drivers/media/video/cx88/cx88-reg.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/media/video/cx88/cx88-reg.h b/drivers/media/video/cx88/cx88-reg.h index 2b1d102cd22..2ec52d1cdea 100644 --- a/drivers/media/video/cx88/cx88-reg.h +++ b/drivers/media/video/cx88/cx88-reg.h @@ -612,6 +612,19 @@ #define SEL_FMRADIO 0x20 // AUD_CTL +#define AUD_INT_DN_RISCI1 (1 << 0) +#define AUD_INT_UP_RISCI1 (1 << 1) +#define AUD_INT_RDS_DN_RISCI1 (1 << 2) +#define AUD_INT_DN_RISCI2 (1 << 4) /* yes, 3 is skipped */ +#define AUD_INT_UP_RISCI2 (1 << 5) +#define AUD_INT_RDS_DN_RISCI2 (1 << 6) +#define AUD_INT_DN_SYNC (1 << 12) +#define AUD_INT_UP_SYNC (1 << 13) +#define AUD_INT_RDS_DN_SYNC (1 << 14) +#define AUD_INT_OPC_ERR (1 << 16) +#define AUD_INT_BER_IRQ (1 << 20) +#define AUD_INT_MCHG_IRQ (1 << 21) + #define EN_BTSC_FORCE_MONO 0 #define EN_BTSC_FORCE_STEREO 1 #define EN_BTSC_FORCE_SAP 2 |