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authorHyeonsu Kim <hyeonsu.kim@samsung.com>2013-02-22 09:32:46 +0900
committerChris Ball <cjb@laptop.org>2013-03-22 12:03:22 -0400
commitc69042a51e7d890c373345a7e524e895b266eb72 (patch)
tree338448164f9f80284776775dea8d4f0e25de14c4 /drivers/mmc/host/dw_mmc.c
parent87a74d399a165510b053c406699992af9add0da9 (diff)
mmc: dw_mmc: fixed a wrong UHS_REG 16 bit clear
In the legacy code, driver clear not only UHS_REG 16 bit also 0-15bit. If we use UHS-1 mode spec card like SDR50, SDR104. UHS_REG 0-15 should be set by 1 according to slot id. In this case, legacy code can cause problems. In particular, UHS_REG consists of DDR_REG[31:16] and VOLT_REG[15:0]. Before adjusting this patch, bit[15:0] is always cleared. Signed-off-by: Hyeonsu Kim <hyeonsu.kim@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc/host/dw_mmc.c')
-rw-r--r--drivers/mmc/host/dw_mmc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 2f4a62ffb22..38732d85009 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -795,9 +795,9 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
/* DDR mode set */
if (ios->timing == MMC_TIMING_UHS_DDR50)
- regs |= (0x1 << slot->id) << 16;
+ regs |= ((0x1 << slot->id) << 16);
else
- regs &= ~(0x1 << slot->id) << 16;
+ regs &= ~((0x1 << slot->id) << 16);
mci_writel(slot->host, UHS_REG, regs);