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authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>2013-07-10 21:21:13 +0200
committerChris Ball <cjb@laptop.org>2013-08-25 00:10:18 -0400
commit6d6fd3674259d16b735c961743ff28870c46cedc (patch)
treeb93ef646e4343d7ba4baad0ace663b562bbfb01f /drivers/mmc
parent967bcb77177cda1a426fdb2350e6ec61bcf5b5eb (diff)
mmc: sh_mmcif: revision-specific CLK_CTRL2 handling
Some newer MMCIF IP revisions contain a CE_CLK_CTRL2 register, that has to be set for proper operation. Support for this feature is added in a way to preserve the current behaviour by default, i.e. when it is not enabled in platform data. Patch is based on work by Nobuyuki HIRAI. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sh_mmcif.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index 6fa6868d103..36629a024aa 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -247,6 +247,7 @@ struct sh_mmcif_host {
bool power;
bool card_present;
bool ccs_enable; /* Command Completion Signal support */
+ bool clk_ctrl2_enable;
struct mutex thread_lock;
/* DMA support */
@@ -497,6 +498,8 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
if (host->ccs_enable)
tmp |= SCCSTO_29;
+ if (host->clk_ctrl2_enable)
+ sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
/* byte swap on */
@@ -1398,6 +1401,7 @@ static int sh_mmcif_probe(struct platform_device *pdev)
host->addr = reg;
host->timeout = msecs_to_jiffies(1000);
host->ccs_enable = !pd || !pd->ccs_unsupported;
+ host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
host->pd = pdev;