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authorBrian Norris <computersforpeace@gmail.com>2011-06-23 14:12:08 -0700
committerArtem Bityutskiy <artem.bityutskiy@intel.com>2011-09-11 15:02:13 +0300
commit7854d3f7495b11be1570cd3e2318674d8f9ed797 (patch)
tree78eef0451fbec53ce062a37888ac026f079b56b0 /drivers/mtd/nand/nand_ecc.c
parent15c60a508ab3393e68b7ccb3528981ccacf9c0f9 (diff)
mtd: spelling, capitalization, uniformity
Therefor -> Therefore [Intern], [Internal] -> [INTERN] [REPLACABLE] -> [REPLACEABLE] syndrom, syndom -> syndrome ecc -> ECC buswith -> buswidth endianess -> endianness dont -> don't occures -> occurs independend -> independent wihin -> within erease -> erase blockes -> blocks ... Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Diffstat (limited to 'drivers/mtd/nand/nand_ecc.c')
-rw-r--r--drivers/mtd/nand/nand_ecc.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 271b8e735e8..b7cfe0d3712 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -110,7 +110,7 @@ static const char bitsperbyte[256] = {
/*
* addressbits is a lookup table to filter out the bits from the xor-ed
- * ecc data that identify the faulty location.
+ * ECC data that identify the faulty location.
* this is only used for repairing parity
* see the comments in nand_correct_data for more details
*/
@@ -153,7 +153,7 @@ static const char addressbits[256] = {
* __nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte
* block
* @buf: input buffer with raw data
- * @eccsize: data bytes per ecc step (256 or 512)
+ * @eccsize: data bytes per ECC step (256 or 512)
* @code: output buffer with ECC
*/
void __nand_calculate_ecc(const unsigned char *buf, unsigned int eccsize,
@@ -348,7 +348,7 @@ void __nand_calculate_ecc(const unsigned char *buf, unsigned int eccsize,
rp17 = (par ^ rp16) & 0xff;
/*
- * Finally calculate the ecc bits.
+ * Finally calculate the ECC bits.
* Again here it might seem that there are performance optimisations
* possible, but benchmarks showed that on the system this is developed
* the code below is the fastest
@@ -436,7 +436,7 @@ EXPORT_SYMBOL(nand_calculate_ecc);
* @buf: raw data read from the chip
* @read_ecc: ECC from the chip
* @calc_ecc: the ECC calculated from raw data
- * @eccsize: data bytes per ecc step (256 or 512)
+ * @eccsize: data bytes per ECC step (256 or 512)
*
* Detect and correct a 1 bit error for eccsize byte block
*/
@@ -505,7 +505,7 @@ int __nand_correct_data(unsigned char *buf,
}
/* count nr of bits; use table lookup, faster than calculating it */
if ((bitsperbyte[b0] + bitsperbyte[b1] + bitsperbyte[b2]) == 1)
- return 1; /* error in ecc data; no action needed */
+ return 1; /* error in ECC data; no action needed */
printk(KERN_ERR "uncorrectable error : ");
return -1;