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authorThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 23:25:53 +0200
committerThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 23:25:53 +0200
commit7abd3ef9875eb2afcdcd4f450680298a2983a55e (patch)
tree64c19d2e5ecca182938acfcb8a172efb7d907d85 /drivers/mtd/nand/ts7250.c
parent3821720d51b5f304d2c33021a82c8da70f6d6ac9 (diff)
[MTD] Refactor NAND hwcontrol to cmd_ctrl
The hwcontrol function enforced a step by step state machine for any kind of hardware chip access. Let the hardware driver know which control bits are set and inform it about a change of the control lines. Let the hardware driver write out the command and address bytes directly. This gives a peformance advantage for address bus controlled chips and simplifies the quirks in the hardware drivers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/mtd/nand/ts7250.c')
-rw-r--r--drivers/mtd/nand/ts7250.c44
1 files changed, 21 insertions, 23 deletions
diff --git a/drivers/mtd/nand/ts7250.c b/drivers/mtd/nand/ts7250.c
index 70bce1b0326..a0b4b1edcb0 100644
--- a/drivers/mtd/nand/ts7250.c
+++ b/drivers/mtd/nand/ts7250.c
@@ -83,31 +83,29 @@ static struct mtd_partition partition_info128[] = {
/*
* hardware specific access to control-lines
+ *
+ * ctrl:
+ * NAND_NCE: bit 0 -> bit 2
+ * NAND_CLE: bit 1 -> bit 1
+ * NAND_ALE: bit 2 -> bit 0
*/
-static void ts7250_hwcontrol(struct mtd_info *mtd, int cmd)
+static void ts7250_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- unsigned long ctrl = TS72XX_NAND_CONTROL_VIRT_BASE;
-
- switch (cmd) {
- case NAND_CTL_SETCLE:
- __raw_writeb(__raw_readb(ctrl) | 0x2, ctrl);
- break;
- case NAND_CTL_CLRCLE:
- __raw_writeb(__raw_readb(ctrl) & ~0x2, ctrl);
- break;
- case NAND_CTL_SETALE:
- __raw_writeb(__raw_readb(ctrl) | 0x1, ctrl);
- break;
- case NAND_CTL_CLRALE:
- __raw_writeb(__raw_readb(ctrl) & ~0x1, ctrl);
- break;
- case NAND_CTL_SETNCE:
- __raw_writeb(__raw_readb(ctrl) | 0x4, ctrl);
- break;
- case NAND_CTL_CLRNCE:
- __raw_writeb(__raw_readb(ctrl) & ~0x4, ctrl);
- break;
+ struct nand_chip *chip = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ unsigned long addr = TS72XX_NAND_CONTROL_VIRT_BASE;
+ unsigned char bits;
+
+ bits = (ctrl & NAND_CNE) << 2;
+ bits |= ctrl & NAND_CLE;
+ bits |= (ctrl & NAND_ALE) >> 2;
+
+ __raw_writeb((__raw_readb(addr) & ~0x7) | bits, addr);
}
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, chip->IO_ADDR_W);
}
/*
@@ -152,7 +150,7 @@ static int __init ts7250_init(void)
/* insert callbacks */
this->IO_ADDR_R = (void *)TS72XX_NAND_DATA_VIRT_BASE;
this->IO_ADDR_W = (void *)TS72XX_NAND_DATA_VIRT_BASE;
- this->hwcontrol = ts7250_hwcontrol;
+ this->cmd_ctrl = ts7250_hwcontrol;
this->dev_ready = ts7250_device_ready;
this->chip_delay = 15;
this->ecc.mode = NAND_ECC_SOFT;