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authorMichael Chan <mchan@broadcom.com>2008-02-23 19:48:57 -0800
committerDavid S. Miller <davem@davemloft.net>2008-02-23 19:48:57 -0800
commit38ea3686f6d1110a3787dfd7c5cf7bad1926818b (patch)
tree9fcbc871ef493c4f718959ffe7a268a82eacc925 /drivers/net/bnx2.c
parenta2724e2559a3c41ac6182da6e2446d3abf0720a5 (diff)
[BNX2]: Disable parallel detect on an HP blade.
Because of some board issues, we need to disable parallel detect on an HP blade. Without this patch, the link state can become stuck when it goes into parallel detect mode. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 2fa25805096..35356fba5a7 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -5362,11 +5362,15 @@ bnx2_test_intr(struct bnx2 *bp)
return -ENODEV;
}
+/* Determining link for parallel detection. */
static int
bnx2_5706_serdes_has_link(struct bnx2 *bp)
{
u32 mode_ctl, an_dbg, exp;
+ if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
+ return 0;
+
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
@@ -7328,7 +7332,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
bp->flags |= BNX2_FLAG_NO_WOL;
bp->wol = 0;
}
- if (CHIP_NUM(bp) != CHIP_NUM_5706) {
+ if (CHIP_NUM(bp) == CHIP_NUM_5706) {
+ /* Don't do parallel detect on this board because of
+ * some board problems. The link will not go down
+ * if we do parallel detect.
+ */
+ if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
+ pdev->subsystem_device == 0x310c)
+ bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
+ } else {
bp->phy_addr = 2;
if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;