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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-04-07 06:03:04 -0700
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-10 19:54:39 -0700
commitadfc5217e9db68d3f0cec8dd847c1a6d3ab549ee (patch)
tree4082ae79d2d4d40b39c9b5144b8171464b5f7eb2 /drivers/net/bnx2_fw.h
parent644570b830266ff33ff5f3542b9c838f93a55ea6 (diff)
broadcom: Move the Broadcom drivers
Moves the drivers for Broadcom devices into drivers/net/ethernet/broadcom/ and the necessary Kconfig and Makefile changes. CC: Eilon Greenstein <eilong@broadcom.com> CC: Michael Chan <mchan@broadcom.com> CC: Matt Carlson <mcarlson@broadcom.com> CC: Gary Zambrano <zambrano@broadcom.com> CC: "Maciej W. Rozycki" <macro@linux-mips.org> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/bnx2_fw.h')
-rw-r--r--drivers/net/bnx2_fw.h88
1 files changed, 0 insertions, 88 deletions
diff --git a/drivers/net/bnx2_fw.h b/drivers/net/bnx2_fw.h
deleted file mode 100644
index 940eb91f209..00000000000
--- a/drivers/net/bnx2_fw.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* bnx2_fw.h: Broadcom NX2 network driver.
- *
- * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
- */
-
-/* Initialized Values for the Completion Processor. */
-static const struct cpu_reg cpu_reg_com = {
- .mode = BNX2_COM_CPU_MODE,
- .mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
- .mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
- .state = BNX2_COM_CPU_STATE,
- .state_value_clear = 0xffffff,
- .gpr0 = BNX2_COM_CPU_REG_FILE,
- .evmask = BNX2_COM_CPU_EVENT_MASK,
- .pc = BNX2_COM_CPU_PROGRAM_COUNTER,
- .inst = BNX2_COM_CPU_INSTRUCTION,
- .bp = BNX2_COM_CPU_HW_BREAKPOINT,
- .spad_base = BNX2_COM_SCRATCH,
- .mips_view_base = 0x8000000,
-};
-
-/* Initialized Values the Command Processor. */
-static const struct cpu_reg cpu_reg_cp = {
- .mode = BNX2_CP_CPU_MODE,
- .mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
- .mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
- .state = BNX2_CP_CPU_STATE,
- .state_value_clear = 0xffffff,
- .gpr0 = BNX2_CP_CPU_REG_FILE,
- .evmask = BNX2_CP_CPU_EVENT_MASK,
- .pc = BNX2_CP_CPU_PROGRAM_COUNTER,
- .inst = BNX2_CP_CPU_INSTRUCTION,
- .bp = BNX2_CP_CPU_HW_BREAKPOINT,
- .spad_base = BNX2_CP_SCRATCH,
- .mips_view_base = 0x8000000,
-};
-
-/* Initialized Values for the RX Processor. */
-static const struct cpu_reg cpu_reg_rxp = {
- .mode = BNX2_RXP_CPU_MODE,
- .mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
- .mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
- .state = BNX2_RXP_CPU_STATE,
- .state_value_clear = 0xffffff,
- .gpr0 = BNX2_RXP_CPU_REG_FILE,
- .evmask = BNX2_RXP_CPU_EVENT_MASK,
- .pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
- .inst = BNX2_RXP_CPU_INSTRUCTION,
- .bp = BNX2_RXP_CPU_HW_BREAKPOINT,
- .spad_base = BNX2_RXP_SCRATCH,
- .mips_view_base = 0x8000000,
-};
-
-/* Initialized Values for the TX Patch-up Processor. */
-static const struct cpu_reg cpu_reg_tpat = {
- .mode = BNX2_TPAT_CPU_MODE,
- .mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
- .mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
- .state = BNX2_TPAT_CPU_STATE,
- .state_value_clear = 0xffffff,
- .gpr0 = BNX2_TPAT_CPU_REG_FILE,
- .evmask = BNX2_TPAT_CPU_EVENT_MASK,
- .pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
- .inst = BNX2_TPAT_CPU_INSTRUCTION,
- .bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
- .spad_base = BNX2_TPAT_SCRATCH,
- .mips_view_base = 0x8000000,
-};
-
-/* Initialized Values for the TX Processor. */
-static const struct cpu_reg cpu_reg_txp = {
- .mode = BNX2_TXP_CPU_MODE,
- .mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
- .mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
- .state = BNX2_TXP_CPU_STATE,
- .state_value_clear = 0xffffff,
- .gpr0 = BNX2_TXP_CPU_REG_FILE,
- .evmask = BNX2_TXP_CPU_EVENT_MASK,
- .pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
- .inst = BNX2_TXP_CPU_INSTRUCTION,
- .bp = BNX2_TXP_CPU_HW_BREAKPOINT,
- .spad_base = BNX2_TXP_SCRATCH,
- .mips_view_base = 0x8000000,
-};