diff options
| author | Eilon Greenstein <eilong@broadcom.com> | 2009-02-12 08:37:07 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-02-15 23:31:36 -0800 |
| commit | c1b7399027254a45a4036c548c13eb97c7d0d8fa (patch) | |
| tree | e4c6b5d2b9964174e003dcc51795ea519b8efb18 /drivers/net/bnx2x_reg.h | |
| parent | 811a2f2d3be9a39bd4e0930501fda8630857748d (diff) | |
bnx2x: Using the HW 5th lane
This 1G interface (on top of the 4 lanes 10G interface) requires additional
setting to work in CL45
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_reg.h')
| -rw-r--r-- | drivers/net/bnx2x_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index b6c924934a0..d3086e92470 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h @@ -1815,6 +1815,10 @@ #define NIG_REG_PRS_EOP_OUT_EN 0x10104 /* [RW 1] Input enable for RX parser request IF */ #define NIG_REG_PRS_REQ_IN_EN 0x100b8 +/* [RW 5] control to serdes - CL45 DEVAD */ +#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 +/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ +#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ |