diff options
| author | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2011-04-07 06:57:17 -0700 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2011-08-10 19:54:52 -0700 |
| commit | f7917c009c28c941ba151ee66f04dc7f6a2e1e0b (patch) | |
| tree | 91cd66b3b846b1113654de2ac31f085d0d7989ba /drivers/net/chelsio | |
| parent | adfc5217e9db68d3f0cec8dd847c1a6d3ab549ee (diff) | |
chelsio: Move the Chelsio drivers
Moves the drivers for the Chelsio chipsets into
drivers/net/ethernet/chelsio/ and the necessary Kconfig and Makefile
changes.
CC: Divy Le Ray <divy@chelsio.com>
CC: Dimitris Michailidis <dm@chelsio.com>
CC: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/chelsio')
24 files changed, 0 insertions, 13762 deletions
diff --git a/drivers/net/chelsio/Makefile b/drivers/net/chelsio/Makefile deleted file mode 100644 index 57a4b262fd3..00000000000 --- a/drivers/net/chelsio/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Chelsio T1 driver -# - -obj-$(CONFIG_CHELSIO_T1) += cxgb.o - -cxgb-$(CONFIG_CHELSIO_T1_1G) += mv88e1xxx.o vsc7326.o -cxgb-objs := cxgb2.o espi.o tp.o pm3393.o sge.o subr.o \ - mv88x201x.o my3126.o $(cxgb-y) diff --git a/drivers/net/chelsio/common.h b/drivers/net/chelsio/common.h deleted file mode 100644 index 5ccbed1784d..00000000000 --- a/drivers/net/chelsio/common.h +++ /dev/null @@ -1,353 +0,0 @@ -/***************************************************************************** - * * - * File: common.h * - * $Revision: 1.21 $ * - * $Date: 2005/06/22 00:43:25 $ * - * Description: * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#define pr_fmt(fmt) "cxgb: " fmt - -#ifndef _CXGB_COMMON_H_ -#define _CXGB_COMMON_H_ - -#include <linux/module.h> -#include <linux/netdevice.h> -#include <linux/types.h> -#include <linux/delay.h> -#include <linux/pci.h> -#include <linux/ethtool.h> -#include <linux/if_vlan.h> -#include <linux/mdio.h> -#include <linux/crc32.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <asm/io.h> -#include <linux/pci_ids.h> - -#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver" -#define DRV_NAME "cxgb" -#define DRV_VERSION "2.2" - -#define CH_DEVICE(devid, ssid, idx) \ - { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx } - -#define SUPPORTED_PAUSE (1 << 13) -#define SUPPORTED_LOOPBACK (1 << 15) - -#define ADVERTISED_PAUSE (1 << 13) -#define ADVERTISED_ASYM_PAUSE (1 << 14) - -typedef struct adapter adapter_t; - -struct t1_rx_mode { - struct net_device *dev; -}; - -#define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC) -#define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI) -#define t1_rx_mode_mc_cnt(rm) (netdev_mc_count(rm->dev)) -#define t1_get_netdev(rm) (rm->dev) - -#define MAX_NPORTS 4 -#define PORT_MASK ((1 << MAX_NPORTS) - 1) -#define NMTUS 8 -#define TCB_SIZE 128 - -#define SPEED_INVALID 0xffff -#define DUPLEX_INVALID 0xff - -enum { - CHBT_BOARD_N110, - CHBT_BOARD_N210, - CHBT_BOARD_7500, - CHBT_BOARD_8000, - CHBT_BOARD_CHT101, - CHBT_BOARD_CHT110, - CHBT_BOARD_CHT210, - CHBT_BOARD_CHT204, - CHBT_BOARD_CHT204V, - CHBT_BOARD_CHT204E, - CHBT_BOARD_CHN204, - CHBT_BOARD_COUGAR, - CHBT_BOARD_6800, - CHBT_BOARD_SIMUL, -}; - -enum { - CHBT_TERM_FPGA, - CHBT_TERM_T1, - CHBT_TERM_T2, - CHBT_TERM_T3 -}; - -enum { - CHBT_MAC_CHELSIO_A, - CHBT_MAC_IXF1010, - CHBT_MAC_PM3393, - CHBT_MAC_VSC7321, - CHBT_MAC_DUMMY -}; - -enum { - CHBT_PHY_88E1041, - CHBT_PHY_88E1111, - CHBT_PHY_88X2010, - CHBT_PHY_XPAK, - CHBT_PHY_MY3126, - CHBT_PHY_8244, - CHBT_PHY_DUMMY -}; - -enum { - PAUSE_RX = 1 << 0, - PAUSE_TX = 1 << 1, - PAUSE_AUTONEG = 1 << 2 -}; - -/* Revisions of T1 chip */ -enum { - TERM_T1A = 0, - TERM_T1B = 1, - TERM_T2 = 3 -}; - -struct sge_params { - unsigned int cmdQ_size[2]; - unsigned int freelQ_size[2]; - unsigned int large_buf_capacity; - unsigned int rx_coalesce_usecs; - unsigned int last_rx_coalesce_raw; - unsigned int default_rx_coalesce_usecs; - unsigned int sample_interval_usecs; - unsigned int coalesce_enable; - unsigned int polling; -}; - -struct chelsio_pci_params { - unsigned short speed; - unsigned char width; - unsigned char is_pcix; -}; - -struct tp_params { - unsigned int pm_size; - unsigned int cm_size; - unsigned int pm_rx_base; - unsigned int pm_tx_base; - unsigned int pm_rx_pg_size; - unsigned int pm_tx_pg_size; - unsigned int pm_rx_num_pgs; - unsigned int pm_tx_num_pgs; - unsigned int rx_coalescing_size; - unsigned int use_5tuple_mode; -}; - -struct mc5_params { - unsigned int mode; /* selects MC5 width */ - unsigned int nservers; /* size of server region */ - unsigned int nroutes; /* size of routing region */ -}; - -/* Default MC5 region sizes */ -#define DEFAULT_SERVER_REGION_LEN 256 -#define DEFAULT_RT_REGION_LEN 1024 - -struct adapter_params { - struct sge_params sge; - struct mc5_params mc5; - struct tp_params tp; - struct chelsio_pci_params pci; - - const struct board_info *brd_info; - - unsigned short mtus[NMTUS]; - unsigned int nports; /* # of ethernet ports */ - unsigned int stats_update_period; - unsigned short chip_revision; - unsigned char chip_version; - unsigned char is_asic; - unsigned char has_msi; -}; - -struct link_config { - unsigned int supported; /* link capabilities */ - unsigned int advertising; /* advertised capabilities */ - unsigned short requested_speed; /* speed user has requested */ - unsigned short speed; /* actual link speed */ - unsigned char requested_duplex; /* duplex user has requested */ - unsigned char duplex; /* actual link duplex */ - unsigned char requested_fc; /* flow control user has requested */ - unsigned char fc; /* actual link flow control */ - unsigned char autoneg; /* autonegotiating? */ -}; - -struct cmac; -struct cphy; - -struct port_info { - struct net_device *dev; - struct cmac *mac; - struct cphy *phy; - struct link_config link_config; - struct net_device_stats netstats; -}; - -struct sge; -struct peespi; - -struct adapter { - u8 __iomem *regs; - struct pci_dev *pdev; - unsigned long registered_device_map; - unsigned long open_device_map; - unsigned long flags; - - const char *name; - int msg_enable; - u32 mmio_len; - - struct work_struct ext_intr_handler_task; - struct adapter_params params; - - /* Terminator modules. */ - struct sge *sge; - struct peespi *espi; - struct petp *tp; - - struct napi_struct napi; - struct port_info port[MAX_NPORTS]; - struct delayed_work stats_update_task; - struct timer_list stats_update_timer; - - spinlock_t tpi_lock; - spinlock_t work_lock; - spinlock_t mac_lock; - - /* guards async operations */ - spinlock_t async_lock ____cacheline_aligned; - u32 slow_intr_mask; - int t1powersave; -}; - -enum { /* adapter flags */ - FULL_INIT_DONE = 1 << 0, -}; - -struct mdio_ops; -struct gmac; -struct gphy; - -struct board_info { - unsigned char board; - unsigned char port_number; - unsigned long caps; - unsigned char chip_term; - unsigned char chip_mac; - unsigned char chip_phy; - unsigned int clock_core; - unsigned int clock_mc3; - unsigned int clock_mc4; - unsigned int espi_nports; - unsigned int clock_elmer0; - unsigned char mdio_mdien; - unsigned char mdio_mdiinv; - unsigned char mdio_mdc; - unsigned char mdio_phybaseaddr; - const struct gmac *gmac; - const struct gphy *gphy; - const struct mdio_ops *mdio_ops; - const char *desc; -}; - -static inline int t1_is_asic(const adapter_t *adapter) -{ - return adapter->params.is_asic; -} - -extern const struct pci_device_id t1_pci_tbl[]; - -static inline int adapter_matches_type(const adapter_t *adapter, - int version, int revision) -{ - return adapter->params.chip_version == version && - adapter->params.chip_revision == revision; -} - -#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B) -#define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2) - -/* Returns true if an adapter supports VLAN acceleration and TSO */ -static inline int vlan_tso_capable(const adapter_t *adapter) -{ - return !t1_is_T1B(adapter); -} - -#define for_each_port(adapter, iter) \ - for (iter = 0; iter < (adapter)->params.nports; ++iter) - -#define board_info(adapter) ((adapter)->params.brd_info) -#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full) - -static inline unsigned int core_ticks_per_usec(const adapter_t *adap) -{ - return board_info(adap)->clock_core / 1000000; -} - -extern int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp); -extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value); -extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value); -extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value); - -extern void t1_interrupts_enable(adapter_t *adapter); -extern void t1_interrupts_disable(adapter_t *adapter); -extern void t1_interrupts_clear(adapter_t *adapter); -extern int t1_elmer0_ext_intr_handler(adapter_t *adapter); -extern void t1_elmer0_ext_intr(adapter_t *adapter); -extern int t1_slow_intr_handler(adapter_t *adapter); - -extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); -extern const struct board_info *t1_get_board_info(unsigned int board_id); -extern const struct board_info *t1_get_board_info_from_ids(unsigned int devid, - unsigned short ssid); -extern int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data); -extern int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi, - struct adapter_params *p); -extern int t1_init_hw_modules(adapter_t *adapter); -extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi); -extern void t1_free_sw_modules(adapter_t *adapter); -extern void t1_fatal_err(adapter_t *adapter); -extern void t1_link_changed(adapter_t *adapter, int port_id); -extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat, - int speed, int duplex, int pause); -#endif /* _CXGB_COMMON_H_ */ diff --git a/drivers/net/chelsio/cphy.h b/drivers/net/chelsio/cphy.h deleted file mode 100644 index 1f095a9fc73..00000000000 --- a/drivers/net/chelsio/cphy.h +++ /dev/null @@ -1,175 +0,0 @@ -/***************************************************************************** - * * - * File: cphy.h * - * $Revision: 1.7 $ * - * $Date: 2005/06/21 18:29:47 $ * - * Description: * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#ifndef _CXGB_CPHY_H_ -#define _CXGB_CPHY_H_ - -#include "common.h" - -struct mdio_ops { - void (*init)(adapter_t *adapter, const struct board_info *bi); - int (*read)(struct net_device *dev, int phy_addr, int mmd_addr, - u16 reg_addr); - int (*write)(struct net_device *dev, int phy_addr, int mmd_addr, - u16 reg_addr, u16 val); - unsigned mode_support; -}; - -/* PHY interrupt types */ -enum { - cphy_cause_link_change = 0x1, - cphy_cause_error = 0x2, - cphy_cause_fifo_error = 0x3 -}; - -enum { - PHY_LINK_UP = 0x1, - PHY_AUTONEG_RDY = 0x2, - PHY_AUTONEG_EN = 0x4 -}; - -struct cphy; - -/* PHY operations */ -struct cphy_ops { - void (*destroy)(struct cphy *); - int (*reset)(struct cphy *, int wait); - - int (*interrupt_enable)(struct cphy *); - int (*interrupt_disable)(struct cphy *); - int (*interrupt_clear)(struct cphy *); - int (*interrupt_handler)(struct cphy *); - - int (*autoneg_enable)(struct cphy *); - int (*autoneg_disable)(struct cphy *); - int (*autoneg_restart)(struct cphy *); - - int (*advertise)(struct cphy *phy, unsigned int advertise_map); - int (*set_loopback)(struct cphy *, int on); - int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); - int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, - int *duplex, int *fc); - - u32 mmds; -}; - -/* A PHY instance */ -struct cphy { - int state; /* Link status state machine */ - adapter_t *adapter; /* associated adapter */ - - struct delayed_work phy_update; - - u16 bmsr; - int count; - int act_count; - int act_on; - - u32 elmer_gpo; - - const struct cphy_ops *ops; /* PHY operations */ - struct mdio_if_info mdio; - struct cphy_instance *instance; -}; - -/* Convenience MDIO read/write wrappers */ -static inline int cphy_mdio_read(struct cphy *cphy, int mmd, int reg, - unsigned int *valp) -{ - int rc = cphy->mdio.mdio_read(cphy->mdio.dev, cphy->mdio.prtad, mmd, - reg); - *valp = (rc >= 0) ? rc : -1; - return (rc >= 0) ? 0 : rc; -} - -static inline int cphy_mdio_write(struct cphy *cphy, int mmd, int reg, - unsigned int val) -{ - return cphy->mdio.mdio_write(cphy->mdio.dev, cphy->mdio.prtad, mmd, - reg, val); -} - -static inline int simple_mdio_read(struct cphy *cphy, int reg, - unsigned int *valp) -{ - return cphy_mdio_read(cphy, MDIO_DEVAD_NONE, reg, valp); -} - -static inline int simple_mdio_write(struct cphy *cphy, int reg, - unsigned int val) -{ - return cphy_mdio_write(cphy, MDIO_DEVAD_NONE, reg, val); -} - -/* Convenience initializer */ -static inline void cphy_init(struct cphy *phy, struct net_device *dev, - int phy_addr, struct cphy_ops *phy_ops, - const struct mdio_ops *mdio_ops) -{ - struct adapter *adapter = netdev_priv(dev); - phy->adapter = adapter; - phy->ops = phy_ops; - if (mdio_ops) { - phy->mdio.prtad = phy_addr; - phy->mdio.mmds = phy_ops->mmds; - phy->mdio.mode_support = mdio_ops->mode_support; - phy->mdio.mdio_read = mdio_ops->read; - phy->mdio.mdio_write = mdio_ops->write; - } - phy->mdio.dev = dev; -} - -/* Operations of the PHY-instance factory */ -struct gphy { - /* Construct a PHY instance with the given PHY address */ - struct cphy *(*create)(struct net_device *dev, int phy_addr, - const struct mdio_ops *mdio_ops); - - /* - * Reset the PHY chip. This resets the whole PHY chip, not individual - * ports. - */ - int (*reset)(adapter_t *adapter); -}; - -extern const struct gphy t1_my3126_ops; -extern const struct gphy t1_mv88e1xxx_ops; -extern const struct gphy t1_vsc8244_ops; -extern const struct gphy t1_mv88x201x_ops; - -#endif /* _CXGB_CPHY_H_ */ diff --git a/drivers/net/chelsio/cpl5_cmd.h b/drivers/net/chelsio/cpl5_cmd.h deleted file mode 100644 index e36d45b78cc..00000000000 --- a/drivers/net/chelsio/cpl5_cmd.h +++ /dev/null @@ -1,639 +0,0 @@ -/***************************************************************************** - * * - * File: cpl5_cmd.h * - * $Revision: 1.6 $ * - * $Date: 2005/06/21 18:29:47 $ * - * Description: * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#ifndef _CXGB_CPL5_CMD_H_ -#define _CXGB_CPL5_CMD_H_ - -#include <asm/byteorder.h> - -#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD) -#error "Adjust your <asm/byteorder.h> defines" -#endif - -enum CPL_opcode { - CPL_PASS_OPEN_REQ = 0x1, - CPL_PASS_OPEN_RPL = 0x2, - CPL_PASS_ESTABLISH = 0x3, - CPL_PASS_ACCEPT_REQ = 0xE, - CPL_PASS_ACCEPT_RPL = 0x4, - CPL_ACT_OPEN_REQ = 0x5, - CPL_ACT_OPEN_RPL = 0x6, - CPL_CLOSE_CON_REQ = 0x7, - CPL_CLOSE_CON_RPL = 0x8, - CPL_CLOSE_LISTSRV_REQ = 0x9, - CPL_CLOSE_LISTSRV_RPL = 0xA, - CPL_ABORT_REQ = 0xB, - CPL_ABORT_RPL = 0xC, - CPL_PEER_CLOSE = 0xD, - CPL_ACT_ESTABLISH = 0x17, - - CPL_GET_TCB = 0x24, - CPL_GET_TCB_RPL = 0x25, - CPL_SET_TCB = 0x26, - CPL_SET_TCB_FIELD = 0x27, - CPL_SET_TCB_RPL = 0x28, - CPL_PCMD = 0x29, - - CPL_PCMD_READ = 0x31, - CPL_PCMD_READ_RPL = 0x32, - - - CPL_RX_DATA = 0xA0, - CPL_RX_DATA_DDP = 0xA1, - CPL_RX_DATA_ACK = 0xA3, - CPL_RX_PKT = 0xAD, - CPL_RX_ISCSI_HDR = 0xAF, - CPL_TX_DATA_ACK = 0xB0, - CPL_TX_DATA = 0xB1, - CPL_TX_PKT = 0xB2, - CPL_TX_PKT_LSO = 0xB6, - - CPL_RTE_DELETE_REQ = 0xC0, - CPL_RTE_DELETE_RPL = 0xC1, - CPL_RTE_WRITE_REQ = 0xC2, - CPL_RTE_WRITE_RPL = 0xD3, - CPL_RTE_READ_REQ = 0xC3, - CPL_RTE_READ_RPL = 0xC4, - CPL_L2T_WRITE_REQ = 0xC5, - CPL_L2T_WRITE_RPL = 0xD4, - CPL_L2T_READ_REQ = 0xC6, - CPL_L2T_READ_RPL = 0xC7, - CPL_SMT_WRITE_REQ = 0xC8, - CPL_SMT_WRITE_RPL = 0xD5, - CPL_SMT_READ_REQ = 0xC9, - CPL_SMT_READ_RPL = 0xCA, - CPL_ARP_MISS_REQ = 0xCD, - CPL_ARP_MISS_RPL = 0xCE, - CPL_MIGRATE_C2T_REQ = 0xDC, - CPL_MIGRATE_C2T_RPL = 0xDD, - CPL_ERROR = 0xD7, - - /* internal: driver -> TOM */ - CPL_MSS_CHANGE = 0xE1 -}; - -#define NUM_CPL_CMDS 256 - -enum CPL_error { - CPL_ERR_NONE = 0, - CPL_ERR_TCAM_PARITY = 1, - CPL_ERR_TCAM_FULL = 3, - CPL_ERR_CONN_RESET = 20, - CPL_ERR_CONN_EXIST = 22, - CPL_ERR_ARP_MISS = 23, - CPL_ERR_BAD_SYN = 24, - CPL_ERR_CONN_TIMEDOUT = 30, - CPL_ERR_XMIT_TIMEDOUT = 31, - CPL_ERR_PERSIST_TIMEDOUT = 32, - CPL_ERR_FINWAIT2_TIMEDOUT = 33, - CPL_ERR_KEEPALIVE_TIMEDOUT = 34, - CPL_ERR_ABORT_FAILED = 42, - CPL_ERR_GENERAL = 99 -}; - -enum { - CPL_CONN_POLICY_AUTO = 0, - CPL_CONN_POLICY_ASK = 1, - CPL_CONN_POLICY_DENY = 3 -}; - -enum { - ULP_MODE_NONE = 0, - ULP_MODE_TCPDDP = 1, - ULP_MODE_ISCSI = 2, - ULP_MODE_IWARP = 3, - ULP_MODE_SSL = 4 -}; - -enum { - CPL_PASS_OPEN_ACCEPT, - CPL_PASS_OPEN_REJECT -}; - -enum { - CPL_ABORT_SEND_RST = 0, - CPL_ABORT_NO_RST, - CPL_ABORT_POST_CLOSE_REQ = 2 -}; - -enum { // TX_PKT_LSO ethernet types - CPL_ETH_II, - CPL_ETH_II_VLAN, - CPL_ETH_802_3, - CPL_ETH_802_3_VLAN -}; - -union opcode_tid { - u32 opcode_tid; - u8 opcode; -}; - -#define S_OPCODE 24 -#define V_OPCODE(x) ((x) << S_OPCODE) -#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) -#define G_TID(x) ((x) & 0xFFFFFF) - -/* tid is assumed to be 24-bits */ -#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) - -#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) - -/* extract the TID from a CPL command */ -#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) - -struct tcp_options { - u16 mss; - u8 wsf; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 rsvd:4; - u8 ecn:1; - u8 sack:1; - u8 tstamp:1; -#else - u8 tstamp:1; - u8 sack:1; - u8 ecn:1; - u8 rsvd:4; -#endif -}; - -struct cpl_pass_open_req { - union opcode_tid ot; - u16 local_port; - u16 peer_port; - u32 local_ip; - u32 peer_ip; - u32 opt0h; - u32 opt0l; - u32 peer_netmask; - u32 opt1; -}; - -struct cpl_pass_open_rpl { - union opcode_tid ot; - u16 local_port; - u16 peer_port; - u32 local_ip; - u32 peer_ip; - u8 resvd[7]; - u8 status; -}; - -struct cpl_pass_establish { - union opcode_tid ot; - u16 local_port; - u16 peer_port; - u32 local_ip; - u32 peer_ip; - u32 tos_tid; - u8 l2t_idx; - u8 rsvd[3]; - u32 snd_isn; - u32 rcv_isn; -}; - -struct cpl_pass_accept_req { - union opcode_tid ot; - u16 local_port; - u16 peer_port; - u32 local_ip; - u32 peer_ip; - u32 tos_tid; - struct tcp_options tcp_options; - u8 dst_mac[6]; - u16 vlan_tag; - u8 src_mac[6]; - u8 rsvd[2]; - u32 rcv_isn; - u32 unknown_tcp_options; -}; - -struct cpl_pass_accept_rpl { - union opcode_tid ot; - u32 rsvd0; - u32 rsvd1; - u32 peer_ip; - u32 opt0h; - union { - u32 opt0l; - struct { - u8 rsvd[3]; - u8 status; - }; - }; -}; - -struct cpl_act_open_req { - union opcode_tid ot; - u16 local_port; - u16 peer_port; - u32 local_ip; - u32 peer_ip; - u32 opt0h; - u32 opt0l; - u32 iff_vlantag; - u32 rsvd; -}; - -struct cpl_act_open_rpl { - union opcode_tid ot; - u16 local_port; - u16 peer_port; - u32 local_ip; - u32 peer_ip; - u32 new_tid; - u8 rsvd[3]; - u8 status; -}; - -struct cpl_act_establish { - union opcode_tid ot; - u16 local_port; - u16 peer_port; - u32 local_ip; - u32 peer_ip; - u32 tos_tid; - u32 rsvd; - u32 snd_isn; - u32 rcv_isn; -}; - -struct cpl_get_tcb { - union opcode_tid ot; - u32 rsvd; -}; - -struct cpl_get_tcb_rpl { - union opcode_tid ot; - u16 len; - u8 rsvd; - u8 status; -}; - -struct cpl_set_tcb { - union opcode_tid ot; - u16 len; - u16 rsvd; -}; - -struct cpl_set_tcb_field { - union opcode_tid ot; - u8 rsvd[3]; - u8 offset; - u32 mask; - u32 val; -}; - -struct cpl_set_tcb_rpl { - union opcode_tid ot; - u8 rsvd[3]; - u8 status; -}; - -struct cpl_pcmd { - union opcode_tid ot; - u16 dlen_in; - u16 dlen_out; - u32 pcmd_parm[2]; -}; - -struct cpl_pcmd_read { - union opcode_tid ot; - u32 rsvd1; - u16 rsvd2; - u32 addr; - u16 len; -}; - -struct cpl_pcmd_read_rpl { - union opcode_tid ot; - u16 len; -}; - -struct cpl_close_con_req { - union opcode_tid ot; - u32 rsvd; -}; - -struct cpl_close_con_rpl { - union opcode_tid ot; - u8 rsvd[3]; - u8 status; - u32 snd_nxt; - u32 rcv_nxt; -}; - -struct cpl_close_listserv_req { - union opcode_tid ot; - u32 rsvd; -}; - -struct cpl_close_listserv_rpl { - union opcode_tid ot; - u8 rsvd[3]; - u8 status; -}; - -struct cpl_abort_req { - union opcode_tid ot; - u32 rsvd0; - u8 rsvd1; - u8 cmd; - u8 rsvd2[6]; -}; - -struct cpl_abort_rpl { - union opcode_tid ot; - u32 rsvd0; - u8 rsvd1; - u8 status; - u8 rsvd2[6]; -}; - -struct cpl_peer_close { - union opcode_tid ot; - u32 rsvd; -}; - -struct cpl_tx_data { - union opcode_tid ot; - u32 len; - u32 rsvd0; - u16 urg; - u16 flags; -}; - -struct cpl_tx_data_ack { - union opcode_tid ot; - u32 ack_seq; -}; - -struct cpl_rx_data { - union opcode_tid ot; - u32 len; - u32 seq; - u16 urg; - u8 rsvd; - u8 status; -}; - -struct cpl_rx_data_ack { - union opcode_tid ot; - u32 credit; -}; - -struct cpl_rx_data_ddp { - union opcode_tid ot; - u32 len; - u32 seq; - u32 nxt_seq; - u32 ulp_crc; - u16 ddp_status; - u8 rsvd; - u8 status; -}; - -/* - * We want this header's alignment to be no more stringent than 2-byte aligned. - * All fields are u8 or u16 except for the length. However that field is not - * used so we break it into 2 16-bit parts to easily meet our alignment needs. - */ -struct cpl_tx_pkt { - u8 opcode; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 iff:4; - u8 ip_csum_dis:1; - u8 l4_csum_dis:1; - u8 vlan_valid:1; - u8 rsvd:1; -#else - u8 rsvd:1; - u8 vlan_valid:1; - u8 l4_csum_dis:1; - u8 ip_csum_dis:1; - u8 iff:4; -#endif - u16 vlan; - u16 len_hi; - u16 len_lo; -}; - -struct cpl_tx_pkt_lso { - u8 opcode; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 iff:4; - u8 ip_csum_dis:1; - u8 l4_csum_dis:1; - u8 vlan_valid:1; - u8 :1; -#else - u8 :1; - u8 vlan_valid:1; - u8 l4_csum_dis:1; - u8 ip_csum_dis:1; - u8 iff:4; -#endif - u16 vlan; - __be32 len; - - u8 rsvd[5]; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 tcp_hdr_words:4; - u8 ip_hdr_words:4; -#else - u8 ip_hdr_words:4; - u8 tcp_hdr_words:4; -#endif - __be16 eth_type_mss; -}; - -struct cpl_rx_pkt { - u8 opcode; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 iff:4; - u8 csum_valid:1; - u8 bad_pkt:1; - u8 vlan_valid:1; - u8 rsvd:1; -#else - u8 rsvd:1; - u8 vlan_valid:1; - u8 bad_pkt:1; - u8 csum_valid:1; - u8 iff:4; -#endif - u16 csum; - u16 vlan; - u16 len; -}; - -struct cpl_l2t_write_req { - union opcode_tid ot; - u32 params; - u8 rsvd1[2]; - u8 dst_mac[6]; -}; - -struct cpl_l2t_write_rpl { - union opcode_tid ot; - u8 status; - u8 rsvd[3]; -}; - -struct cpl_l2t_read_req { - union opcode_tid ot; - u8 rsvd[3]; - u8 l2t_idx; -}; - -struct cpl_l2t_read_rpl { - union opcode_tid ot; - u32 params; - u8 rsvd1[2]; - u8 dst_mac[6]; -}; - -struct cpl_smt_write_req { - union opcode_tid ot; - u8 rsvd0; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 rsvd1:1; - u8 mtu_idx:3; - u8 iff:4; -#else - u8 iff:4; - u8 mtu_idx:3; - u8 rsvd1:1; -#endif - u16 rsvd2; - u16 rsvd3; - u8 src_mac1[6]; - u16 rsvd4; - u8 src_mac0[6]; -}; - -struct cpl_smt_write_rpl { - union opcode_tid ot; - u8 status; - u8 rsvd[3]; -}; - -struct cpl_smt_read_req { - union opcode_tid ot; - u8 rsvd0; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 rsvd1:4; - u8 iff:4; -#else - u8 iff:4; - u8 rsvd1:4; -#endif - u16 rsvd2; -}; - -struct cpl_smt_read_rpl { - union opcode_tid ot; - u8 status; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 rsvd1:1; - u8 mtu_idx:3; - u8 rsvd0:4; -#else - u8 rsvd0:4; - u8 mtu_idx:3; - u8 rsvd1:1; -#endif - u16 rsvd2; - u16 rsvd3; - u8 src_mac1[6]; - u16 rsvd4; - u8 src_mac0[6]; -}; - -struct cpl_rte_delete_req { - union opcode_tid ot; - u32 params; -}; - -struct cpl_rte_delete_rpl { - union opcode_tid ot; - u8 status; - u8 rsvd[3]; -}; - -struct cpl_rte_write_req { - union opcode_tid ot; - u32 params; - u32 netmask; - u32 faddr; -}; - -struct cpl_rte_write_rpl { - union opcode_tid ot; - u8 status; - u8 rsvd[3]; -}; - -struct cpl_rte_read_req { - union opcode_tid ot; - u32 params; -}; - -struct cpl_rte_read_rpl { - union opcode_tid ot; - u8 status; - u8 rsvd0[2]; - u8 l2t_idx; -#if defined(__LITTLE_ENDIAN_BITFIELD) - u8 rsvd1:7; - u8 select:1; -#else - u8 select:1; - u8 rsvd1:7; -#endif - u8 rsvd2[3]; - u32 addr; -}; - -struct cpl_mss_change { - union opcode_tid ot; - u32 mss; -}; - -#endif /* _CXGB_CPL5_CMD_H_ */ - diff --git a/drivers/net/chelsio/cxgb2.c b/drivers/net/chelsio/cxgb2.c deleted file mode 100644 index 3edbbc4c511..00000000000 --- a/drivers/net/chelsio/cxgb2.c +++ /dev/null @@ -1,1379 +0,0 @@ -/***************************************************************************** - * * - * File: cxgb2.c * - * $Revision: 1.25 $ * - * $Date: 2005/06/22 00:43:25 $ * - * Description: * - * Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#include "common.h" -#include <linux/module.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/netdevice.h> -#include <linux/etherdevice.h> -#include <linux/if_vlan.h> -#include <linux/mii.h> -#include <linux/sockios.h> -#include <linux/dma-mapping.h> -#include <asm/uaccess.h> - -#include "cpl5_cmd.h" -#include "regs.h" -#include "gmac.h" -#include "cphy.h" -#include "sge.h" -#include "tp.h" -#include "espi.h" -#include "elmer0.h" - -#include <linux/workqueue.h> - -static inline void schedule_mac_stats_update(struct adapter *ap, int secs) -{ - schedule_delayed_work(&ap->stats_update_task, secs * HZ); -} - -static inline void cancel_mac_stats_update(struct adapter *ap) -{ - cancel_delayed_work(&ap->stats_update_task); -} - -#define MAX_CMDQ_ENTRIES 16384 -#define MAX_CMDQ1_ENTRIES 1024 -#define MAX_RX_BUFFERS 16384 -#define MAX_RX_JUMBO_BUFFERS 16384 -#define MAX_TX_BUFFERS_HIGH 16384U -#define MAX_TX_BUFFERS_LOW 1536U -#define MAX_TX_BUFFERS 1460U -#define MIN_FL_ENTRIES 32 - -#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ - NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ - NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) - -/* - * The EEPROM is actually bigger but only the first few bytes are used so we - * only report those. - */ -#define EEPROM_SIZE 32 - -MODULE_DESCRIPTION(DRV_DESCRIPTION); -MODULE_AUTHOR("Chelsio Communications"); -MODULE_LICENSE("GPL"); - -static int dflt_msg_enable = DFLT_MSG_ENABLE; - -module_param(dflt_msg_enable, int, 0); -MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T1 default message enable bitmap"); - -#define HCLOCK 0x0 -#define LCLOCK 0x1 - -/* T1 cards powersave mode */ -static int t1_clock(struct adapter *adapter, int mode); -static int t1powersave = 1; /* HW default is powersave mode. */ - -module_param(t1powersave, int, 0); -MODULE_PARM_DESC(t1powersave, "Enable/Disable T1 powersaving mode"); - -static int disable_msi = 0; -module_param(disable_msi, int, 0); -MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); - -static const char pci_speed[][4] = { - "33", "66", "100", "133" -}; - -/* - * Setup MAC to receive the types of packets we want. - */ -static void t1_set_rxmode(struct net_device *dev) -{ - struct adapter *adapter = dev->ml_priv; - struct cmac *mac = adapter->port[dev->if_port].mac; - struct t1_rx_mode rm; - - rm.dev = dev; - mac->ops->set_rx_mode(mac, &rm); -} - -static void link_report(struct port_info *p) -{ - if (!netif_carrier_ok(p->dev)) - printk(KERN_INFO "%s: link down\n", p->dev->name); - else { - const char *s = "10Mbps"; - - switch (p->link_config.speed) { - case SPEED_10000: s = "10Gbps"; break; - case SPEED_1000: s = "1000Mbps"; break; - case SPEED_100: s = "100Mbps"; break; - } - - printk(KERN_INFO "%s: link up, %s, %s-duplex\n", - p->dev->name, s, - p->link_config.duplex == DUPLEX_FULL ? "full" : "half"); - } -} - -void t1_link_negotiated(struct adapter *adapter, int port_id, int link_stat, - int speed, int duplex, int pause) -{ - struct port_info *p = &adapter->port[port_id]; - - if (link_stat != netif_carrier_ok(p->dev)) { - if (link_stat) - netif_carrier_on(p->dev); - else - netif_carrier_off(p->dev); - link_report(p); - - /* multi-ports: inform toe */ - if ((speed > 0) && (adapter->params.nports > 1)) { - unsigned int sched_speed = 10; - switch (speed) { - case SPEED_1000: - sched_speed = 1000; - break; - case SPEED_100: - sched_speed = 100; - break; - case SPEED_10: - sched_speed = 10; - break; - } - t1_sched_update_parms(adapter->sge, port_id, 0, sched_speed); - } - } -} - -static void link_start(struct port_info *p) -{ - struct cmac *mac = p->mac; - - mac->ops->reset(mac); - if (mac->ops->macaddress_set) - mac->ops->macaddress_set(mac, p->dev->dev_addr); - t1_set_rxmode(p->dev); - t1_link_start(p->phy, mac, &p->link_config); - mac->ops->enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); -} - -static void enable_hw_csum(struct adapter *adapter) -{ - if (adapter->port[0].dev->hw_features & NETIF_F_TSO) - t1_tp_set_ip_checksum_offload(adapter->tp, 1); /* for TSO only */ - t1_tp_set_tcp_checksum_offload(adapter->tp, 1); -} - -/* - * Things to do upon first use of a card. - * This must run with the rtnl lock held. - */ -static int cxgb_up(struct adapter *adapter) -{ - int err = 0; - - if (!(adapter->flags & FULL_INIT_DONE)) { - err = t1_init_hw_modules(adapter); - if (err) - goto out_err; - - enable_hw_csum(adapter); - adapter->flags |= FULL_INIT_DONE; - } - - t1_interrupts_clear(adapter); - - adapter->params.has_msi = !disable_msi && !pci_enable_msi(adapter->pdev); - err = request_irq(adapter->pdev->irq, t1_interrupt, - adapter->params.has_msi ? 0 : IRQF_SHARED, - adapter->name, adapter); - if (err) { - if (adapter->params.has_msi) - pci_disable_msi(adapter->pdev); - - goto out_err; - } - - t1_sge_start(adapter->sge); - t1_interrupts_enable(adapter); -out_err: - return err; -} - -/* - * Release resources when all the ports have been stopped. - */ -static void cxgb_down(struct adapter *adapter) -{ - t1_sge_stop(adapter->sge); - t1_interrupts_disable(adapter); - free_irq(adapter->pdev->irq, adapter); - if (adapter->params.has_msi) - pci_disable_msi(adapter->pdev); -} - -static int cxgb_open(struct net_device *dev) -{ - int err; - struct adapter *adapter = dev->ml_priv; - int other_ports = adapter->open_device_map & PORT_MASK; - - napi_enable(&adapter->napi); - if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0) { - napi_disable(&adapter->napi); - return err; - } - - __set_bit(dev->if_port, &adapter->open_device_map); - link_start(&adapter->port[dev->if_port]); - netif_start_queue(dev); - if (!other_ports && adapter->params.stats_update_period) - schedule_mac_stats_update(adapter, - adapter->params.stats_update_period); - - t1_vlan_mode(adapter, dev->features); - return 0; -} - -static int cxgb_close(struct net_device *dev) -{ - struct adapter *adapter = dev->ml_priv; - struct port_info *p = &adapter->port[dev->if_port]; - struct cmac *mac = p->mac; - - netif_stop_queue(dev); - napi_disable(&adapter->napi); - mac->ops->disable(mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); - netif_carrier_off(dev); - - clear_bit(dev->if_port, &adapter->open_device_map); - if (adapter->params.stats_update_period && - !(adapter->open_device_map & PORT_MASK)) { - /* Stop statistics accumulation. */ - smp_mb__after_clear_bit(); - spin_lock(&adapter->work_lock); /* sync with update task */ - spin_unlock(&adapter->work_lock); - cancel_mac_stats_update(adapter); - } - - if (!adapter->open_device_map) - cxgb_down(adapter); - return 0; -} - -static struct net_device_stats *t1_get_stats(struct net_device *dev) -{ - struct adapter *adapter = dev->ml_priv; - struct port_info *p = &adapter->port[dev->if_port]; - struct net_device_stats *ns = &p->netstats; - const struct cmac_statistics *pstats; - - /* Do a full update of the MAC stats */ - pstats = p->mac->ops->statistics_update(p->mac, - MAC_STATS_UPDATE_FULL); - - ns->tx_packets = pstats->TxUnicastFramesOK + - pstats->TxMulticastFramesOK + pstats->TxBroadcastFramesOK; - - ns->rx_packets = pstats->RxUnicastFramesOK + - pstats->RxMulticastFramesOK + pstats->RxBroadcastFramesOK; - - ns->tx_bytes = pstats->TxOctetsOK; - ns->rx_bytes = pstats->RxOctetsOK; - - ns->tx_errors = pstats->TxLateCollisions + pstats->TxLengthErrors + - pstats->TxUnderrun + pstats->TxFramesAbortedDueToXSCollisions; - ns->rx_errors = pstats->RxDataErrors + pstats->RxJabberErrors + - pstats->RxFCSErrors + pstats->RxAlignErrors + - pstats->RxSequenceErrors + pstats->RxFrameTooLongErrors + - pstats->RxSymbolErrors + pstats->RxRuntErrors; - - ns->multicast = pstats->RxMulticastFramesOK; - ns->collisions = pstats->TxTotalCollisions; - - /* detailed rx_errors */ - ns->rx_length_errors = pstats->RxFrameTooLongErrors + - pstats->RxJabberErrors; - ns->rx_over_errors = 0; - ns->rx_crc_errors = pstats->RxFCSErrors; - ns->rx_frame_errors = pstats->RxAlignErrors; - ns->rx_fifo_errors = 0; - ns->rx_missed_errors = 0; - - /* detailed tx_errors */ - ns->tx_aborted_errors = pstats->TxFramesAbortedDueToXSCollisions; - ns->tx_carrier_errors = 0; - ns->tx_fifo_errors = pstats->TxUnderrun; - ns->tx_heartbeat_errors = 0; - ns->tx_window_errors = pstats->TxLateCollisions; - return ns; -} - -static u32 get_msglevel(struct net_device *dev) -{ - struct adapter *adapter = dev->ml_priv; - - return adapter->msg_enable; -} - -static void set_msglevel(struct net_device *dev, u32 val) -{ - struct adapter *adapter = dev->ml_priv; - - adapter->msg_enable = val; -} - -static char stats_strings[][ETH_GSTRING_LEN] = { - "TxOctetsOK", - "TxOctetsBad", - "TxUnicastFramesOK", - "TxMulticastFramesOK", - "TxBroadcastFramesOK", - "TxPauseFrames", - "TxFramesWithDeferredXmissions", - "TxLateCollisions", - "TxTotalCollisions", - "TxFramesAbortedDueToXSCollisions", - "TxUnderrun", - "TxLengthErrors", - "TxInternalMACXmitError", - "TxFramesWithExcessiveDeferral", - "TxFCSErrors", - "TxJumboFramesOk", - "TxJumboOctetsOk", - - "RxOctetsOK", - "RxOctetsBad", - "RxUnicastFramesOK", - "RxMulticastFramesOK", - "RxBroadcastFramesOK", - "RxPauseFrames", - "RxFCSErrors", - "RxAlignErrors", - "RxSymbolErrors", - "RxDataErrors", - "RxSequenceErrors", - "RxRuntErrors", - "RxJabberErrors", - "RxInternalMACRcvError", - "RxInRangeLengthErrors", - "RxOutOfRangeLengthField", - "RxFrameTooLongErrors", - "RxJumboFramesOk", - "RxJumboOctetsOk", - - /* Port stats */ - "RxCsumGood", - "TxCsumOffload", - "TxTso", - "RxVlan", - "TxVlan", - "TxNeedHeadroom", - - /* Interrupt stats */ - "rx drops", - "pure_rsps", - "unhandled irqs", - "respQ_empty", - "respQ_overflow", - "freelistQ_empty", - "pkt_too_big", - "pkt_mismatch", - "cmdQ_full0", - "cmdQ_full1", - - "espi_DIP2ParityErr", - "espi_DIP4Err", - "espi_RxDrops", - "espi_TxDrops", - "espi_RxOvfl", - "espi_ParityErr" -}; - -#define T2_REGMAP_SIZE (3 * 1024) - -static int get_regs_len(struct net_device *dev) -{ - return T2_REGMAP_SIZE; -} - -static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) -{ - struct adapter *adapter = dev->ml_priv; - - strcpy(info->driver, DRV_NAME); - strcpy(info->version, DRV_VERSION); - strcpy(info->fw_version, "N/A"); - strcpy(info->bus_info, pci_name(adapter->pdev)); -} - -static int get_sset_count(struct net_device *dev, int sset) -{ - switch (sset) { - case ETH_SS_STATS: - return ARRAY_SIZE(stats_strings); - default: - return -EOPNOTSUPP; - } -} - -static void get_strings(struct net_device *dev, u32 stringset, u8 *data) -{ - if (stringset == ETH_SS_STATS) - memcpy(data, stats_strings, sizeof(stats_strings)); -} - -static void get_stats(struct net_device *dev, struct ethtool_stats *stats, - u64 *data) -{ - struct adapter *adapter = dev->ml_priv; - struct cmac *mac = adapter->port[dev->if_port].mac; - const struct cmac_statistics *s; - const struct sge_intr_counts *t; - struct sge_port_stats ss; - - s = mac->ops->statistics_update(mac, MAC_STATS_UPDATE_FULL); - t = t1_sge_get_intr_counts(adapter->sge); - t1_sge_get_port_stats(adapter->sge, dev->if_port, &ss); - - *data++ = s->TxOctetsOK; - *data++ = s->TxOctetsBad; - *data++ = s->TxUnicastFramesOK; - *data++ = s->TxMulticastFramesOK; - *data++ = s->TxBroadcastFramesOK; - *data++ = s->TxPauseFrames; - *data++ = s->TxFramesWithDeferredXmissions; - *data++ = s->TxLateCollisions; - *data++ = s->TxTotalCollisions; - *data++ = s->TxFramesAbortedDueToXSCollisions; - *data++ = s->TxUnderrun; - *data++ = s->TxLengthErrors; - *data++ = s->TxInternalMACXmitError; - *data++ = s->TxFramesWithExcessiveDeferral; - *data++ = s->TxFCSErrors; - *data++ = s->TxJumboFramesOK; - *data++ = s->TxJumboOctetsOK; - - *data++ = s->RxOctetsOK; - *data++ = s->RxOctetsBad; - *data++ = s->RxUnicastFramesOK; - *data++ = s->RxMulticastFramesOK; - *data++ = s->RxBroadcastFramesOK; - *data++ = s->RxPauseFrames; - *data++ = s->RxFCSErrors; - *data++ = s->RxAlignErrors; - *data++ = s->RxSymbolErrors; - *data++ = s->RxDataErrors; - *data++ = s->RxSequenceErrors; - *data++ = s->RxRuntErrors; - *data++ = s->RxJabberErrors; - *data++ = s->RxInternalMACRcvError; - *data++ = s->RxInRangeLengthErrors; - *data++ = s->RxOutOfRangeLengthField; - *data++ = s->RxFrameTooLongErrors; - *data++ = s->RxJumboFramesOK; - *data++ = s->RxJumboOctetsOK; - - *data++ = ss.rx_cso_good; - *data++ = ss.tx_cso; - *data++ = ss.tx_tso; - *data++ = ss.vlan_xtract; - *data++ = ss.vlan_insert; - *data++ = ss.tx_need_hdrroom; - - *data++ = t->rx_drops; - *data++ = t->pure_rsps; - *data++ = t->unhandled_irqs; - *data++ = t->respQ_empty; - *data++ = t->respQ_overflow; - *data++ = t->freelistQ_empty; - *data++ = t->pkt_too_big; - *data++ = t->pkt_mismatch; - *data++ = t->cmdQ_full[0]; - *data++ = t->cmdQ_full[1]; - - if (adapter->espi) { - const struct espi_intr_counts *e; - - e = t1_espi_get_intr_counts(adapter->espi); - *data++ = e->DIP2_parity_err; - *data++ = e->DIP4_err; - *data++ = e->rx_drops; - *data++ = e->tx_drops; - *data++ = e->rx_ovflw; - *data++ = e->parity_err; - } -} - -static inline void reg_block_dump(struct adapter *ap, void *buf, - unsigned int start, unsigned int end) -{ - u32 *p = buf + start; - - for ( ; start <= end; start += sizeof(u32)) - *p++ = readl(ap->regs + start); -} - -static void get_regs(struct net_device *dev, struct ethtool_regs *regs, - void *buf) -{ - struct adapter *ap = dev->ml_priv; - - /* - * Version scheme: bits 0..9: chip version, bits 10..15: chip revision - */ - regs->version = 2; - - memset(buf, 0, T2_REGMAP_SIZE); - reg_block_dump(ap, buf, 0, A_SG_RESPACCUTIMER); - reg_block_dump(ap, buf, A_MC3_CFG, A_MC4_INT_CAUSE); - reg_block_dump(ap, buf, A_TPI_ADDR, A_TPI_PAR); - reg_block_dump(ap, buf, A_TP_IN_CONFIG, A_TP_TX_DROP_COUNT); - reg_block_dump(ap, buf, A_RAT_ROUTE_CONTROL, A_RAT_INTR_CAUSE); - reg_block_dump(ap, buf, A_CSPI_RX_AE_WM, A_CSPI_INTR_ENABLE); - reg_block_dump(ap, buf, A_ESPI_SCH_TOKEN0, A_ESPI_GOSTAT); - reg_block_dump(ap, buf, A_ULP_ULIMIT, A_ULP_PIO_CTRL); - reg_block_dump(ap, buf, A_PL_ENABLE, A_PL_CAUSE); - reg_block_dump(ap, buf, A_MC5_CONFIG, A_MC5_MASK_WRITE_CMD); -} - -static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd) -{ - struct adapter *adapter = dev->ml_priv; - struct port_info *p = &adapter->port[dev->if_port]; - - cmd->supported = p->link_config.supported; - cmd->advertising = p->link_config.advertising; - - if (netif_carrier_ok(dev)) { - ethtool_cmd_speed_set(cmd, p->link_config.speed); - cmd->duplex = p->link_config.duplex; - } else { - ethtool_cmd_speed_set(cmd, -1); - cmd->duplex = -1; - } - - cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE; - cmd->phy_address = p->phy->mdio.prtad; - cmd->transceiver = XCVR_EXTERNAL; - cmd->autoneg = p->link_config.autoneg; - cmd->maxtxpkt = 0; - cmd->maxrxpkt = 0; - return 0; -} - -static int speed_duplex_to_caps(int speed, int duplex) -{ - int cap = 0; - - switch (speed) { - case SPEED_10: - if (duplex == DUPLEX_FULL) - cap = SUPPORTED_10baseT_Full; - else - cap = SUPPORTED_10baseT_Half; - break; - case SPEED_100: - if (duplex == DUPLEX_FULL) - cap = SUPPORTED_100baseT_Full; - else - cap = SUPPORTED_100baseT_Half; - break; - case SPEED_1000: - if (duplex == DUPLEX_FULL) - cap = SUPPORTED_1000baseT_Full; - else - cap = SUPPORTED_1000baseT_Half; - break; - case SPEED_10000: - if (duplex == DUPLEX_FULL) - cap = SUPPORTED_10000baseT_Full; - } - return cap; -} - -#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ - ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ - ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \ - ADVERTISED_10000baseT_Full) - -static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd) -{ - struct adapter *adapter = dev->ml_priv; - struct port_info *p = &adapter->port[dev->if_port]; - struct link_config *lc = &p->link_config; - - if (!(lc->supported & SUPPORTED_Autoneg)) - return -EOPNOTSUPP; /* can't change speed/duplex */ - - if (cmd->autoneg == AUTONEG_DISABLE) { - u32 speed = ethtool_cmd_speed(cmd); - int cap = speed_duplex_to_caps(speed, cmd->duplex); - - if (!(lc->supported & cap) || (speed == SPEED_1000)) - return -EINVAL; - lc->requested_speed = speed; - lc->requested_duplex = cmd->duplex; - lc->advertising = 0; - } else { - cmd->advertising &= ADVERTISED_MASK; - if (cmd->advertising & (cmd->advertising - 1)) - cmd->advertising = lc->supported; - cmd->advertising &= lc->supported; - if (!cmd->advertising) - return -EINVAL; - lc->requested_speed = SPEED_INVALID; - lc->requested_duplex = DUPLEX_INVALID; - lc->advertising = cmd->advertising | ADVERTISED_Autoneg; - } - lc->autoneg = cmd->autoneg; - if (netif_running(dev)) - t1_link_start(p->phy, p->mac, lc); - return 0; -} - -static void get_pauseparam(struct net_device *dev, - struct ethtool_pauseparam *epause) -{ - struct adapter *adapter = dev->ml_priv; - struct port_info *p = &adapter->port[dev->if_port]; - - epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0; - epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0; - epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0; -} - -static int set_pauseparam(struct net_device *dev, - struct ethtool_pauseparam *epause) -{ - struct adapter *adapter = dev->ml_priv; - struct port_info *p = &adapter->port[dev->if_port]; - struct link_config *lc = &p->link_config; - - if (epause->autoneg == AUTONEG_DISABLE) - lc->requested_fc = 0; - else if (lc->supported & SUPPORTED_Autoneg) - lc->requested_fc = PAUSE_AUTONEG; - else - return -EINVAL; - - if (epause->rx_pause) - lc->requested_fc |= PAUSE_RX; - if (epause->tx_pause) - lc->requested_fc |= PAUSE_TX; - if (lc->autoneg == AUTONEG_ENABLE) { - if (netif_running(dev)) - t1_link_start(p->phy, p->mac, lc); - } else { - lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); - if (netif_running(dev)) - p->mac->ops->set_speed_duplex_fc(p->mac, -1, -1, - lc->fc); - } - return 0; -} - -static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e) -{ - struct adapter *adapter = dev->ml_priv; - int jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; - - e->rx_max_pending = MAX_RX_BUFFERS; - e->rx_mini_max_pending = 0; - e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS; - e->tx_max_pending = MAX_CMDQ_ENTRIES; - - e->rx_pending = adapter->params.sge.freelQ_size[!jumbo_fl]; - e->rx_mini_pending = 0; - e->rx_jumbo_pending = adapter->params.sge.freelQ_size[jumbo_fl]; - e->tx_pending = adapter->params.sge.cmdQ_size[0]; -} - -static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e) -{ - struct adapter *adapter = dev->ml_priv; - int jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; - - if (e->rx_pending > MAX_RX_BUFFERS || e->rx_mini_pending || - e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS || - e->tx_pending > MAX_CMDQ_ENTRIES || - e->rx_pending < MIN_FL_ENTRIES || - e->rx_jumbo_pending < MIN_FL_ENTRIES || - e->tx_pending < (adapter->params.nports + 1) * (MAX_SKB_FRAGS + 1)) - return -EINVAL; - - if (adapter->flags & FULL_INIT_DONE) - return -EBUSY; - - adapter->params.sge.freelQ_size[!jumbo_fl] = e->rx_pending; - adapter->params.sge.freelQ_size[jumbo_fl] = e->rx_jumbo_pending; - adapter->params.sge.cmdQ_size[0] = e->tx_pending; - adapter->params.sge.cmdQ_size[1] = e->tx_pending > MAX_CMDQ1_ENTRIES ? - MAX_CMDQ1_ENTRIES : e->tx_pending; - return 0; -} - -static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c) -{ - struct adapter *adapter = dev->ml_priv; - - adapter->params.sge.rx_coalesce_usecs = c->rx_coalesce_usecs; - adapter->params.sge.coalesce_enable = c->use_adaptive_rx_coalesce; - adapter->params.sge.sample_interval_usecs = c->rate_sample_interval; - t1_sge_set_coalesce_params(adapter->sge, &adapter->params.sge); - return 0; -} - -static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c) -{ - struct adapter *adapter = dev->ml_priv; - - c->rx_coalesce_usecs = adapter->params.sge.rx_coalesce_usecs; - c->rate_sample_interval = adapter->params.sge.sample_interval_usecs; - c->use_adaptive_rx_coalesce = adapter->params.sge.coalesce_enable; - return 0; -} - -static int get_eeprom_len(struct net_device *dev) -{ - struct adapter *adapter = dev->ml_priv; - - return t1_is_asic(adapter) ? EEPROM_SIZE : 0; -} - -#define EEPROM_MAGIC(ap) \ - (PCI_VENDOR_ID_CHELSIO | ((ap)->params.chip_version << 16)) - -static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e, - u8 *data) -{ - int i; - u8 buf[EEPROM_SIZE] __attribute__((aligned(4))); - struct adapter *adapter = dev->ml_priv; - - e->magic = EEPROM_MAGIC(adapter); - for (i = e->offset & ~3; i < e->offset + e->len; i += sizeof(u32)) - t1_seeprom_read(adapter, i, (__le32 *)&buf[i]); - memcpy(data, buf + e->offset, e->len); - return 0; -} - -static const struct ethtool_ops t1_ethtool_ops = { - .get_settings = get_settings, - .set_settings = set_settings, - .get_drvinfo = get_drvinfo, - .get_msglevel = get_msglevel, - .set_msglevel = set_msglevel, - .get_ringparam = get_sge_param, - .set_ringparam = set_sge_param, - .get_coalesce = get_coalesce, - .set_coalesce = set_coalesce, - .get_eeprom_len = get_eeprom_len, - .get_eeprom = get_eeprom, - .get_pauseparam = get_pauseparam, - .set_pauseparam = set_pauseparam, - .get_link = ethtool_op_get_link, - .get_strings = get_strings, - .get_sset_count = get_sset_count, - .get_ethtool_stats = get_stats, - .get_regs_len = get_regs_len, - .get_regs = get_regs, -}; - -static int t1_ioctl(struct net_device *dev, struct ifreq *req, int cmd) -{ - struct adapter *adapter = dev->ml_priv; - struct mdio_if_info *mdio = &adapter->port[dev->if_port].phy->mdio; - - return mdio_mii_ioctl(mdio, if_mii(req), cmd); -} - -static int t1_change_mtu(struct net_device *dev, int new_mtu) -{ - int ret; - struct adapter *adapter = dev->ml_priv; - struct cmac *mac = adapter->port[dev->if_port].mac; - - if (!mac->ops->set_mtu) - return -EOPNOTSUPP; - if (new_mtu < 68) - return -EINVAL; - if ((ret = mac->ops->set_mtu(mac, new_mtu))) - return ret; - dev->mtu = new_mtu; - return 0; -} - -static int t1_set_mac_addr(struct net_device *dev, void *p) -{ - struct adapter *adapter = dev->ml_priv; - struct cmac *mac = adapter->port[dev->if_port].mac; - struct sockaddr *addr = p; - - if (!mac->ops->macaddress_set) - return -EOPNOTSUPP; - - memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); - mac->ops->macaddress_set(mac, dev->dev_addr); - return 0; -} - -static u32 t1_fix_features(struct net_device *dev, u32 features) -{ - /* - * Since there is no support for separate rx/tx vlan accel - * enable/disable make sure tx flag is always in same state as rx. - */ - if (features & NETIF_F_HW_VLAN_RX) - features |= NETIF_F_HW_VLAN_TX; - else - features &= ~NETIF_F_HW_VLAN_TX; - - return features; -} - -static int t1_set_features(struct net_device *dev, u32 features) -{ - u32 changed = dev->features ^ features; - struct adapter *adapter = dev->ml_priv; - - if (changed & NETIF_F_HW_VLAN_RX) - t1_vlan_mode(adapter, features); - - return 0; -} -#ifdef CONFIG_NET_POLL_CONTROLLER -static void t1_netpoll(struct net_device *dev) -{ - unsigned long flags; - struct adapter *adapter = dev->ml_priv; - - local_irq_save(flags); - t1_interrupt(adapter->pdev->irq, adapter); - local_irq_restore(flags); -} -#endif - -/* - * Periodic accumulation of MAC statistics. This is used only if the MAC - * does not have any other way to prevent stats counter overflow. - */ -static void mac_stats_task(struct work_struct *work) -{ - int i; - struct adapter *adapter = - container_of(work, struct adapter, stats_update_task.work); - - for_each_port(adapter, i) { - struct port_info *p = &adapter->port[i]; - - if (netif_running(p->dev)) - p->mac->ops->statistics_update(p->mac, - MAC_STATS_UPDATE_FAST); - } - - /* Schedule the next statistics update if any port is active. */ - spin_lock(&adapter->work_lock); - if (adapter->open_device_map & PORT_MASK) - schedule_mac_stats_update(adapter, - adapter->params.stats_update_period); - spin_unlock(&adapter->work_lock); -} - -/* - * Processes elmer0 external interrupts in process context. - */ -static void ext_intr_task(struct work_struct *work) -{ - struct adapter *adapter = - container_of(work, struct adapter, ext_intr_handler_task); - - t1_elmer0_ext_intr_handler(adapter); - - /* Now reenable external interrupts */ - spin_lock_irq(&adapter->async_lock); - adapter->slow_intr_mask |= F_PL_INTR_EXT; - writel(F_PL_INTR_EXT, adapter->regs + A_PL_CAUSE); - writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, - adapter->regs + A_PL_ENABLE); - spin_unlock_irq(&adapter->async_lock); -} - -/* - * Interrupt-context handler for elmer0 external interrupts. - */ -void t1_elmer0_ext_intr(struct adapter *adapter) -{ - /* - * Schedule a task to handle external interrupts as we require - * a process context. We disable EXT interrupts in the interim - * and let the task reenable them when it's done. - */ - adapter->slow_intr_mask &= ~F_PL_INTR_EXT; - writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, - adapter->regs + A_PL_ENABLE); - schedule_work(&adapter->ext_intr_handler_task); -} - -void t1_fatal_err(struct adapter *adapter) -{ - if (adapter->flags & FULL_INIT_DONE) { - t1_sge_stop(adapter->sge); - t1_interrupts_disable(adapter); - } - pr_alert("%s: encountered fatal error, operation suspended\n", - adapter->name); -} - -static const struct net_device_ops cxgb_netdev_ops = { - .ndo_open = cxgb_open, - .ndo_stop = cxgb_close, - .ndo_start_xmit = t1_start_xmit, - .ndo_get_stats = t1_get_stats, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_multicast_list = t1_set_rxmode, - .ndo_do_ioctl = t1_ioctl, - .ndo_change_mtu = t1_change_mtu, - .ndo_set_mac_address = t1_set_mac_addr, - .ndo_fix_features = t1_fix_features, - .ndo_set_features = t1_set_features, -#ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = t1_netpoll, -#endif -}; - -static int __devinit init_one(struct pci_dev *pdev, - const struct pci_device_id *ent) -{ - static int version_printed; - - int i, err, pci_using_dac = 0; - unsigned long mmio_start, mmio_len; - const struct board_info *bi; - struct adapter *adapter = NULL; - struct port_info *pi; - - if (!version_printed) { - printk(KERN_INFO "%s - version %s\n", DRV_DESCRIPTION, - DRV_VERSION); - ++version_printed; - } - - err = pci_enable_device(pdev); - if (err) - return err; - - if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { - pr_err("%s: cannot find PCI device memory base address\n", - pci_name(pdev)); - err = -ENODEV; - goto out_disable_pdev; - } - - if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { - pci_using_dac = 1; - - if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { - pr_err("%s: unable to obtain 64-bit DMA for " - "consistent allocations\n", pci_name(pdev)); - err = -ENODEV; - goto out_disable_pdev; - } - - } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { - pr_err("%s: no usable DMA configuration\n", pci_name(pdev)); - goto out_disable_pdev; - } - - err = pci_request_regions(pdev, DRV_NAME); - if (err) { - pr_err("%s: cannot obtain PCI resources\n", pci_name(pdev)); - goto out_disable_pdev; - } - - pci_set_master(pdev); - - mmio_start = pci_resource_start(pdev, 0); - mmio_len = pci_resource_len(pdev, 0); - bi = t1_get_board_info(ent->driver_data); - - for (i = 0; i < bi->port_number; ++i) { - struct net_device *netdev; - - netdev = alloc_etherdev(adapter ? 0 : sizeof(*adapter)); - if (!netdev) { - err = -ENOMEM; - goto out_free_dev; - } - - SET_NETDEV_DEV(netdev, &pdev->dev); - - if (!adapter) { - adapter = netdev_priv(netdev); - adapter->pdev = pdev; - adapter->port[0].dev = netdev; /* so we don't leak it */ - - adapter->regs = ioremap(mmio_start, mmio_len); - if (!adapter->regs) { - pr_err("%s: cannot map device registers\n", - pci_name(pdev)); - err = -ENOMEM; - goto out_free_dev; - } - - if (t1_get_board_rev(adapter, bi, &adapter->params)) { - err = -ENODEV; /* Can't handle this chip rev */ - goto out_free_dev; - } - - adapter->name = pci_name(pdev); - adapter->msg_enable = dflt_msg_enable; - adapter->mmio_len = mmio_len; - - spin_lock_init(&adapter->tpi_lock); - spin_lock_init(&adapter->work_lock); - spin_lock_init(&adapter->async_lock); - spin_lock_init(&adapter->mac_lock); - - INIT_WORK(&adapter->ext_intr_handler_task, - ext_intr_task); - INIT_DELAYED_WORK(&adapter->stats_update_task, - mac_stats_task); - - pci_set_drvdata(pdev, netdev); - } - - pi = &adapter->port[i]; - pi->dev = netdev; - netif_carrier_off(netdev); - netdev->irq = pdev->irq; - netdev->if_port = i; - netdev->mem_start = mmio_start; - netdev->mem_end = mmio_start + mmio_len - 1; - netdev->ml_priv = adapter; - netdev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | - NETIF_F_RXCSUM; - netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | - NETIF_F_RXCSUM | NETIF_F_LLTX; - - if (pci_using_dac) - netdev->features |= NETIF_F_HIGHDMA; - if (vlan_tso_capable(adapter)) { - netdev->features |= - NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; - netdev->hw_features |= NETIF_F_HW_VLAN_RX; - - /* T204: disable TSO */ - if (!(is_T2(adapter)) || bi->port_number != 4) { - netdev->hw_features |= NETIF_F_TSO; - netdev->features |= NETIF_F_TSO; - } - } - - netdev->netdev_ops = &cxgb_netdev_ops; - netdev->hard_header_len += (netdev->hw_features & NETIF_F_TSO) ? - sizeof(struct cpl_tx_pkt_lso) : sizeof(struct cpl_tx_pkt); - - netif_napi_add(netdev, &adapter->napi, t1_poll, 64); - - SET_ETHTOOL_OPS(netdev, &t1_ethtool_ops); - } - - if (t1_init_sw_modules(adapter, bi) < 0) { - err = -ENODEV; - goto out_free_dev; - } - - /* - * The card is now ready to go. If any errors occur during device - * registration we do not fail the whole card but rather proceed only - * with the ports we manage to register successfully. However we must - * register at least one net device. - */ - for (i = 0; i < bi->port_number; ++i) { - err = register_netdev(adapter->port[i].dev); - if (err) - pr_warning("%s: cannot register net device %s, skipping\n", - pci_name(pdev), adapter->port[i].dev->name); - else { - /* - * Change the name we use for messages to the name of - * the first successfully registered interface. - */ - if (!adapter->registered_device_map) - adapter->name = adapter->port[i].dev->name; - - __set_bit(i, &adapter->registered_device_map); - } - } - if (!adapter->registered_device_map) { - pr_err("%s: could not register any net devices\n", - pci_name(pdev)); - goto out_release_adapter_res; - } - - printk(KERN_INFO "%s: %s (rev %d), %s %dMHz/%d-bit\n", adapter->name, - bi->desc, adapter->params.chip_revision, - adapter->params.pci.is_pcix ? "PCIX" : "PCI", - adapter->params.pci.speed, adapter->params.pci.width); - - /* - * Set the T1B ASIC and memory clocks. - */ - if (t1powersave) - adapter->t1powersave = LCLOCK; /* HW default is powersave mode. */ - else - adapter->t1powersave = HCLOCK; - if (t1_is_T1B(adapter)) - t1_clock(adapter, t1powersave); - - return 0; - -out_release_adapter_res: - t1_free_sw_modules(adapter); -out_free_dev: - if (adapter) { - if (adapter->regs) - iounmap(adapter->regs); - for (i = bi->port_number - 1; i >= 0; --i) - if (adapter->port[i].dev) - free_netdev(adapter->port[i].dev); - } - pci_release_regions(pdev); -out_disable_pdev: - pci_disable_device(pdev); - pci_set_drvdata(pdev, NULL); - return err; -} - -static void bit_bang(struct adapter *adapter, int bitdata, int nbits) -{ - int data; - int i; - u32 val; - - enum { - S_CLOCK = 1 << 3, - S_DATA = 1 << 4 - }; - - for (i = (nbits - 1); i > -1; i--) { - - udelay(50); - - data = ((bitdata >> i) & 0x1); - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - - if (data) - val |= S_DATA; - else - val &= ~S_DATA; - - udelay(50); - - /* Set SCLOCK low */ - val &= ~S_CLOCK; - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - - udelay(50); - - /* Write SCLOCK high */ - val |= S_CLOCK; - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - - } -} - -static int t1_clock(struct adapter *adapter, int mode) -{ - u32 val; - int M_CORE_VAL; - int M_MEM_VAL; - - enum { - M_CORE_BITS = 9, - T_CORE_VAL = 0, - T_CORE_BITS = 2, - N_CORE_VAL = 0, - N_CORE_BITS = 2, - M_MEM_BITS = 9, - T_MEM_VAL = 0, - T_MEM_BITS = 2, - N_MEM_VAL = 0, - N_MEM_BITS = 2, - NP_LOAD = 1 << 17, - S_LOAD_MEM = 1 << 5, - S_LOAD_CORE = 1 << 6, - S_CLOCK = 1 << 3 - }; - - if (!t1_is_T1B(adapter)) - return -ENODEV; /* Can't re-clock this chip. */ - - if (mode & 2) - return 0; /* show current mode. */ - - if ((adapter->t1powersave & 1) == (mode & 1)) - return -EALREADY; /* ASIC already running in mode. */ - - if ((mode & 1) == HCLOCK) { - M_CORE_VAL = 0x14; - M_MEM_VAL = 0x18; - adapter->t1powersave = HCLOCK; /* overclock */ - } else { - M_CORE_VAL = 0xe; - M_MEM_VAL = 0x10; - adapter->t1powersave = LCLOCK; /* underclock */ - } - - /* Don't interrupt this serial stream! */ - spin_lock(&adapter->tpi_lock); - - /* Initialize for ASIC core */ - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val |= NP_LOAD; - udelay(50); - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(50); - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val &= ~S_LOAD_CORE; - val &= ~S_CLOCK; - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(50); - - /* Serial program the ASIC clock synthesizer */ - bit_bang(adapter, T_CORE_VAL, T_CORE_BITS); - bit_bang(adapter, N_CORE_VAL, N_CORE_BITS); - bit_bang(adapter, M_CORE_VAL, M_CORE_BITS); - udelay(50); - - /* Finish ASIC core */ - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val |= S_LOAD_CORE; - udelay(50); - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(50); - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val &= ~S_LOAD_CORE; - udelay(50); - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(50); - - /* Initialize for memory */ - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val |= NP_LOAD; - udelay(50); - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(50); - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val &= ~S_LOAD_MEM; - val &= ~S_CLOCK; - udelay(50); - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(50); - - /* Serial program the memory clock synthesizer */ - bit_bang(adapter, T_MEM_VAL, T_MEM_BITS); - bit_bang(adapter, N_MEM_VAL, N_MEM_BITS); - bit_bang(adapter, M_MEM_VAL, M_MEM_BITS); - udelay(50); - - /* Finish memory */ - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val |= S_LOAD_MEM; - udelay(50); - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(50); - __t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val &= ~S_LOAD_MEM; - udelay(50); - __t1_tpi_write(adapter, A_ELMER0_GPO, val); - - spin_unlock(&adapter->tpi_lock); - - return 0; -} - -static inline void t1_sw_reset(struct pci_dev *pdev) -{ - pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 3); - pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 0); -} - -static void __devexit remove_one(struct pci_dev *pdev) -{ - struct net_device *dev = pci_get_drvdata(pdev); - struct adapter *adapter = dev->ml_priv; - int i; - - for_each_port(adapter, i) { - if (test_bit(i, &adapter->registered_device_map)) - unregister_netdev(adapter->port[i].dev); - } - - t1_free_sw_modules(adapter); - iounmap(adapter->regs); - - while (--i >= 0) { - if (adapter->port[i].dev) - free_netdev(adapter->port[i].dev); - } - - pci_release_regions(pdev); - pci_disable_device(pdev); - pci_set_drvdata(pdev, NULL); - t1_sw_reset(pdev); -} - -static struct pci_driver driver = { - .name = DRV_NAME, - .id_table = t1_pci_tbl, - .probe = init_one, - .remove = __devexit_p(remove_one), -}; - -static int __init t1_init_module(void) -{ - return pci_register_driver(&driver); -} - -static void __exit t1_cleanup_module(void) -{ - pci_unregister_driver(&driver); -} - -module_init(t1_init_module); -module_exit(t1_cleanup_module); diff --git a/drivers/net/chelsio/elmer0.h b/drivers/net/chelsio/elmer0.h deleted file mode 100644 index eef655c827d..00000000000 --- a/drivers/net/chelsio/elmer0.h +++ /dev/null @@ -1,158 +0,0 @@ -/***************************************************************************** - * * - * File: elmer0.h * - * $Revision: 1.6 $ * - * $Date: 2005/06/21 22:49:43 $ * - * Description: * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#ifndef _CXGB_ELMER0_H_ -#define _CXGB_ELMER0_H_ - -/* ELMER0 flavors */ -enum { - ELMER0_XC2S300E_6FT256_C, - ELMER0_XC2S100E_6TQ144_C -}; - -/* ELMER0 registers */ -#define A_ELMER0_VERSION 0x100000 -#define A_ELMER0_PHY_CFG 0x100004 -#define A_ELMER0_INT_ENABLE 0x100008 -#define A_ELMER0_INT_CAUSE 0x10000c -#define A_ELMER0_GPI_CFG 0x100010 -#define A_ELMER0_GPI_STAT 0x100014 -#define A_ELMER0_GPO 0x100018 -#define A_ELMER0_PORT0_MI1_CFG 0x400000 - -#define S_MI1_MDI_ENABLE 0 -#define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE) -#define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U) - -#define S_MI1_MDI_INVERT 1 -#define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT) -#define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U) - -#define S_MI1_PREAMBLE_ENABLE 2 -#define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE) -#define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U) - -#define S_MI1_SOF 3 -#define M_MI1_SOF 0x3 -#define V_MI1_SOF(x) ((x) << S_MI1_SOF) -#define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF) - -#define S_MI1_CLK_DIV 5 -#define M_MI1_CLK_DIV 0xff -#define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV) -#define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV) - -#define A_ELMER0_PORT0_MI1_ADDR 0x400004 - -#define S_MI1_REG_ADDR 0 -#define M_MI1_REG_ADDR 0x1f -#define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR) -#define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR) - -#define S_MI1_PHY_ADDR 5 -#define M_MI1_PHY_ADDR 0x1f -#define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR) -#define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR) - -#define A_ELMER0_PORT0_MI1_DATA 0x400008 - -#define S_MI1_DATA 0 -#define M_MI1_DATA 0xffff -#define V_MI1_DATA(x) ((x) << S_MI1_DATA) -#define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA) - -#define A_ELMER0_PORT0_MI1_OP 0x40000c - -#define S_MI1_OP 0 -#define M_MI1_OP 0x3 -#define V_MI1_OP(x) ((x) << S_MI1_OP) -#define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP) - -#define S_MI1_ADDR_AUTOINC 2 -#define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC) -#define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U) - -#define S_MI1_OP_BUSY 31 -#define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY) -#define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U) - -#define A_ELMER0_PORT1_MI1_CFG 0x500000 -#define A_ELMER0_PORT1_MI1_ADDR 0x500004 -#define A_ELMER0_PORT1_MI1_DATA 0x500008 -#define A_ELMER0_PORT1_MI1_OP 0x50000c -#define A_ELMER0_PORT2_MI1_CFG 0x600000 -#define A_ELMER0_PORT2_MI1_ADDR 0x600004 -#define A_ELMER0_PORT2_MI1_DATA 0x600008 -#define A_ELMER0_PORT2_MI1_OP 0x60000c -#define A_ELMER0_PORT3_MI1_CFG 0x700000 -#define A_ELMER0_PORT3_MI1_ADDR 0x700004 -#define A_ELMER0_PORT3_MI1_DATA 0x700008 -#define A_ELMER0_PORT3_MI1_OP 0x70000c - -/* Simple bit definition for GPI and GP0 registers. */ -#define ELMER0_GP_BIT0 0x0001 -#define ELMER0_GP_BIT1 0x0002 -#define ELMER0_GP_BIT2 0x0004 -#define ELMER0_GP_BIT3 0x0008 -#define ELMER0_GP_BIT4 0x0010 -#define ELMER0_GP_BIT5 0x0020 -#define ELMER0_GP_BIT6 0x0040 -#define ELMER0_GP_BIT7 0x0080 -#define ELMER0_GP_BIT8 0x0100 -#define ELMER0_GP_BIT9 0x0200 -#define ELMER0_GP_BIT10 0x0400 -#define ELMER0_GP_BIT11 0x0800 -#define ELMER0_GP_BIT12 0x1000 -#define ELMER0_GP_BIT13 0x2000 -#define ELMER0_GP_BIT14 0x4000 -#define ELMER0_GP_BIT15 0x8000 -#define ELMER0_GP_BIT16 0x10000 -#define ELMER0_GP_BIT17 0x20000 -#define ELMER0_GP_BIT18 0x40000 -#define ELMER0_GP_BIT19 0x80000 - -#define MI1_OP_DIRECT_WRITE 1 -#define MI1_OP_DIRECT_READ 2 - -#define MI1_OP_INDIRECT_ADDRESS 0 -#define MI1_OP_INDIRECT_WRITE 1 -#define MI1_OP_INDIRECT_READ_INC 2 -#define MI1_OP_INDIRECT_READ 3 - -#endif /* _CXGB_ELMER0_H_ */ - diff --git a/drivers/net/chelsio/espi.c b/drivers/net/chelsio/espi.c deleted file mode 100644 index 639ff195573..00000000000 --- a/drivers/net/chelsio/espi.c +++ /dev/null @@ -1,373 +0,0 @@ -/***************************************************************************** - * * - * File: espi.c * - * $Revision: 1.14 $ * - * $Date: 2005/05/14 00:59:32 $ * - * Description: * - * Ethernet SPI functionality. * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#include "common.h" -#include "regs.h" -#include "espi.h" - -struct peespi { - adapter_t *adapter; - struct espi_intr_counts intr_cnt; - u32 misc_ctrl; - spinlock_t lock; -}; - -#define ESPI_INTR_MASK (F_DIP4ERR | F_RXDROP | F_TXDROP | F_RXOVERFLOW | \ - F_RAMPARITYERR | F_DIP2PARITYERR) -#define MON_MASK (V_MONITORED_PORT_NUM(3) | F_MONITORED_DIRECTION \ - | F_MONITORED_INTERFACE) - -#define TRICN_CNFG 14 -#define TRICN_CMD_READ 0x11 -#define TRICN_CMD_WRITE 0x21 -#define TRICN_CMD_ATTEMPTS 10 - -static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr, - int ch_addr, int reg_offset, u32 wr_data) -{ - int busy, attempts = TRICN_CMD_ATTEMPTS; - - writel(V_WRITE_DATA(wr_data) | - V_REGISTER_OFFSET(reg_offset) | - V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) | - V_BUNDLE_ADDR(bundle_addr) | - V_SPI4_COMMAND(TRICN_CMD_WRITE), - adapter->regs + A_ESPI_CMD_ADDR); - writel(0, adapter->regs + A_ESPI_GOSTAT); - - do { - busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY; - } while (busy && --attempts); - - if (busy) - pr_err("%s: TRICN write timed out\n", adapter->name); - - return busy; -} - -static int tricn_init(adapter_t *adapter) -{ - int i, sme = 1; - - if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { - pr_err("%s: ESPI clock not ready\n", adapter->name); - return -1; - } - - writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); - - if (sme) { - tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); - tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); - tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); - } - for (i = 1; i <= 8; i++) - tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); - for (i = 1; i <= 2; i++) - tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); - for (i = 1; i <= 3; i++) - tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); - tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); - tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1); - tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1); - tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80); - tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1); - - writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, - adapter->regs + A_ESPI_RX_RESET); - - return 0; -} - -void t1_espi_intr_enable(struct peespi *espi) -{ - u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); - - /* - * Cannot enable ESPI interrupts on T1B because HW asserts the - * interrupt incorrectly, namely the driver gets ESPI interrupts - * but no data is actually dropped (can verify this reading the ESPI - * drop registers). Also, once the ESPI interrupt is asserted it - * cannot be cleared (HW bug). - */ - enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK; - writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); - writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); -} - -void t1_espi_intr_clear(struct peespi *espi) -{ - readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); - writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); - writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); -} - -void t1_espi_intr_disable(struct peespi *espi) -{ - u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); - - writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); - writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); -} - -int t1_espi_intr_handler(struct peespi *espi) -{ - u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); - - if (status & F_DIP4ERR) - espi->intr_cnt.DIP4_err++; - if (status & F_RXDROP) - espi->intr_cnt.rx_drops++; - if (status & F_TXDROP) - espi->intr_cnt.tx_drops++; - if (status & F_RXOVERFLOW) - espi->intr_cnt.rx_ovflw++; - if (status & F_RAMPARITYERR) - espi->intr_cnt.parity_err++; - if (status & F_DIP2PARITYERR) { - espi->intr_cnt.DIP2_parity_err++; - - /* - * Must read the error count to clear the interrupt - * that it causes. - */ - readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); - } - - /* - * For T1B we need to write 1 to clear ESPI interrupts. For T2+ we - * write the status as is. - */ - if (status && t1_is_T1B(espi->adapter)) - status = 1; - writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS); - return 0; -} - -const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi) -{ - return &espi->intr_cnt; -} - -static void espi_setup_for_pm3393(adapter_t *adapter) -{ - u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200; - - writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); - writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1); - writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); - writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3); - writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); - writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); - writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH); - writel(0x08000008, adapter->regs + A_ESPI_TRAIN); - writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); -} - -static void espi_setup_for_vsc7321(adapter_t *adapter) -{ - writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); - writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1); - writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); - writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); - writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); - writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); - writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG); - - writel(0x08000008, adapter->regs + A_ESPI_TRAIN); -} - -/* - * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug. - */ -static void espi_setup_for_ixf1010(adapter_t *adapter, int nports) -{ - writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); - if (nports == 4) { - if (is_T2(adapter)) { - writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); - writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); - } else { - writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); - writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); - } - } else { - writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); - writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); - } - writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG); - -} - -int t1_espi_init(struct peespi *espi, int mac_type, int nports) -{ - u32 status_enable_extra = 0; - adapter_t *adapter = espi->adapter; - - /* Disable ESPI training. MACs that can handle it enable it below. */ - writel(0, adapter->regs + A_ESPI_TRAIN); - - if (is_T2(adapter)) { - writel(V_OUT_OF_SYNC_COUNT(4) | - V_DIP2_PARITY_ERR_THRES(3) | - V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL); - writel(nports == 4 ? 0x200040 : 0x1000080, - adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); - } else - writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); - - if (mac_type == CHBT_MAC_PM3393) - espi_setup_for_pm3393(adapter); - else if (mac_type == CHBT_MAC_VSC7321) - espi_setup_for_vsc7321(adapter); - else if (mac_type == CHBT_MAC_IXF1010) { - status_enable_extra = F_INTEL1010MODE; - espi_setup_for_ixf1010(adapter, nports); - } else - return -1; - - writel(status_enable_extra | F_RXSTATUSENABLE, - adapter->regs + A_ESPI_FIFO_STATUS_ENABLE); - - if (is_T2(adapter)) { - tricn_init(adapter); - /* - * Always position the control at the 1st port egress IN - * (sop,eop) counter to reduce PIOs for T/N210 workaround. - */ - espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL); - espi->misc_ctrl &= ~MON_MASK; - espi->misc_ctrl |= F_MONITORED_DIRECTION; - if (adapter->params.nports == 1) - espi->misc_ctrl |= F_MONITORED_INTERFACE; - writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); - spin_lock_init(&espi->lock); - } - - return 0; -} - -void t1_espi_destroy(struct peespi *espi) -{ - kfree(espi); -} - -struct peespi *t1_espi_create(adapter_t *adapter) -{ - struct peespi *espi = kzalloc(sizeof(*espi), GFP_KERNEL); - - if (espi) - espi->adapter = adapter; - return espi; -} - -#if 0 -void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val) -{ - struct peespi *espi = adapter->espi; - - if (!is_T2(adapter)) - return; - spin_lock(&espi->lock); - espi->misc_ctrl = (val & ~MON_MASK) | - (espi->misc_ctrl & MON_MASK); - writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); - spin_unlock(&espi->lock); -} -#endif /* 0 */ - -u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait) -{ - struct peespi *espi = adapter->espi; - u32 sel; - - if (!is_T2(adapter)) - return 0; - - sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2); - if (!wait) { - if (!spin_trylock(&espi->lock)) - return 0; - } else - spin_lock(&espi->lock); - - if ((sel != (espi->misc_ctrl & MON_MASK))) { - writel(((espi->misc_ctrl & ~MON_MASK) | sel), - adapter->regs + A_ESPI_MISC_CONTROL); - sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); - writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); - } else - sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); - spin_unlock(&espi->lock); - return sel; -} - -/* - * This function is for T204 only. - * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in - * one shot, since there is no per port counter on the out side. - */ -int t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait) -{ - struct peespi *espi = adapter->espi; - u8 i, nport = (u8)adapter->params.nports; - - if (!wait) { - if (!spin_trylock(&espi->lock)) - return -1; - } else - spin_lock(&espi->lock); - - if ((espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION) { - espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) | - F_MONITORED_DIRECTION; - writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); - } - for (i = 0 ; i < nport; i++, valp++) { - if (i) { - writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i), - adapter->regs + A_ESPI_MISC_CONTROL); - } - *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3); - } - - writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); - spin_unlock(&espi->lock); - return 0; -} diff --git a/drivers/net/chelsio/espi.h b/drivers/net/chelsio/espi.h deleted file mode 100644 index 5694aad4fbc..00000000000 --- a/drivers/net/chelsio/espi.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************** - * * - * File: espi.h * - * $Revision: 1.7 $ * - * $Date: 2005/06/21 18:29:47 $ * - * Description: * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#ifndef _CXGB_ESPI_H_ -#define _CXGB_ESPI_H_ - -#include "common.h" - -struct espi_intr_counts { - unsigned int DIP4_err; - unsigned int rx_drops; - unsigned int tx_drops; - unsigned int rx_ovflw; - unsigned int parity_err; - unsigned int DIP2_parity_err; -}; - -struct peespi; - -struct peespi *t1_espi_create(adapter_t *adapter); -void t1_espi_destroy(struct peespi *espi); -int t1_espi_init(struct peespi *espi, int mac_type, int nports); - -void t1_espi_intr_enable(struct peespi *); -void t1_espi_intr_clear(struct peespi *); -void t1_espi_intr_disable(struct peespi *); -int t1_espi_intr_handler(struct peespi *); -const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi); - -u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait); -int t1_espi_get_mon_t204(adapter_t *, u32 *, u8); - -#endif /* _CXGB_ESPI_H_ */ diff --git a/drivers/net/chelsio/fpga_defs.h b/drivers/net/chelsio/fpga_defs.h deleted file mode 100644 index ccdb2bc9ae9..00000000000 --- a/drivers/net/chelsio/fpga_defs.h +++ /dev/null @@ -1,232 +0,0 @@ -/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */ - -/* - * FPGA specific definitions - */ - -#ifndef __CHELSIO_FPGA_DEFS_H__ -#define __CHELSIO_FPGA_DEFS_H__ - -#define FPGA_PCIX_ADDR_VERSION 0xA08 -#define FPGA_PCIX_ADDR_STAT 0xA0C - -/* FPGA master interrupt Cause/Enable bits */ -#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1 -#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2 -#define FPGA_PCIX_INTERRUPT_TP 0x4 -#define FPGA_PCIX_INTERRUPT_MC3 0x8 -#define FPGA_PCIX_INTERRUPT_GMAC 0x10 -#define FPGA_PCIX_INTERRUPT_PCIX 0x20 - -/* TP interrupt register addresses */ -#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10 -#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14 -#define FPGA_TP_ADDR_VERSION 0xA18 - -/* TP interrupt Cause/Enable bits */ -#define FPGA_TP_INTERRUPT_MC4 0x1 -#define FPGA_TP_INTERRUPT_MC5 0x2 - -/* - * PM interrupt register addresses - */ -#define FPGA_MC3_REG_INTRENABLE 0xA20 -#define FPGA_MC3_REG_INTRCAUSE 0xA24 -#define FPGA_MC3_REG_VERSION 0xA28 - -/* - * GMAC interrupt register addresses - */ -#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30 -#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34 -#define FPGA_GMAC_ADDR_VERSION 0xA38 - -/* GMAC Cause/Enable bits */ -#define FPGA_GMAC_INTERRUPT_PORT0 0x1 -#define FPGA_GMAC_INTERRUPT_PORT1 0x2 -#define FPGA_GMAC_INTERRUPT_PORT2 0x4 -#define FPGA_GMAC_INTERRUPT_PORT3 0x8 - -/* MI0 registers */ -#define A_MI0_CLK 0xb00 - -#define S_MI0_CLK_DIV 0 -#define M_MI0_CLK_DIV 0xff -#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV) -#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) - -#define S_MI0_CLK_CNT 8 -#define M_MI0_CLK_CNT 0xff -#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT) -#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) - -#define A_MI0_CSR 0xb04 - -#define S_MI0_CSR_POLL 0 -#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL) -#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U) - -#define S_MI0_PREAMBLE 1 -#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE) -#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U) - -#define S_MI0_INTR_ENABLE 2 -#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE) -#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U) - -#define S_MI0_BUSY 3 -#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY) -#define F_MI0_BUSY V_MI0_BUSY(1U) - -#define S_MI0_MDIO 4 -#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO) -#define F_MI0_MDIO V_MI0_MDIO(1U) - -#define A_MI0_ADDR 0xb08 - -#define S_MI0_PHY_REG_ADDR 0 -#define M_MI0_PHY_REG_ADDR 0x1f -#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR) -#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR) - -#define S_MI0_PHY_ADDR 5 -#define M_MI0_PHY_ADDR 0x1f -#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR) -#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR) - -#define A_MI0_DATA_EXT 0xb0c -#define A_MI0_DATA_INT 0xb10 - -/* GMAC registers */ -#define A_GMAC_MACID_LO 0x28 -#define A_GMAC_MACID_HI 0x2c -#define A_GMAC_CSR 0x30 - -#define S_INTERFACE 0 -#define M_INTERFACE 0x3 -#define V_INTERFACE(x) ((x) << S_INTERFACE) -#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE) - -#define S_MAC_TX_ENABLE 2 -#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE) -#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U) - -#define S_MAC_RX_ENABLE 3 -#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE) -#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U) - -#define S_MAC_LB_ENABLE 4 -#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE) -#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U) - -#define S_MAC_SPEED 5 -#define M_MAC_SPEED 0x3 -#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED) -#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED) - -#define S_MAC_HD_FC_ENABLE 7 -#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE) -#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U) - -#define S_MAC_HALF_DUPLEX 8 -#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX) -#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U) - -#define S_MAC_PROMISC 9 -#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC) -#define F_MAC_PROMISC V_MAC_PROMISC(1U) - -#define S_MAC_MC_ENABLE 10 -#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE) -#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U) - -#define S_MAC_RESET 11 -#define V_MAC_RESET(x) ((x) << S_MAC_RESET) -#define F_MAC_RESET V_MAC_RESET(1U) - -#define S_MAC_RX_PAUSE_ENABLE 12 -#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE) -#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U) - -#define S_MAC_TX_PAUSE_ENABLE 13 -#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE) -#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U) - -#define S_MAC_LWM_ENABLE 14 -#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE) -#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U) - -#define S_MAC_MAGIC_PKT_ENABLE 15 -#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE) -#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U) - -#define S_MAC_ISL_ENABLE 16 -#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE) -#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U) - -#define S_MAC_JUMBO_ENABLE 17 -#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE) -#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U) - -#define S_MAC_RX_PAD_ENABLE 18 -#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE) -#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U) - -#define S_MAC_RX_CRC_ENABLE 19 -#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE) -#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U) - -#define A_GMAC_IFS 0x34 - -#define S_MAC_IFS2 0 -#define M_MAC_IFS2 0x3f -#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2) -#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2) - -#define S_MAC_IFS1 8 -#define M_MAC_IFS1 0x7f -#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1) -#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1) - -#define A_GMAC_JUMBO_FRAME_LEN 0x38 -#define A_GMAC_LNK_DLY 0x3c -#define A_GMAC_PAUSETIME 0x40 -#define A_GMAC_MCAST_LO 0x44 -#define A_GMAC_MCAST_HI 0x48 -#define A_GMAC_MCAST_MASK_LO 0x4c -#define A_GMAC_MCAST_MASK_HI 0x50 -#define A_GMAC_RMT_CNT 0x54 -#define A_GMAC_RMT_DATA 0x58 -#define A_GMAC_BACKOFF_SEED 0x5c -#define A_GMAC_TXF_THRES 0x60 - -#define S_TXF_READ_THRESHOLD 0 -#define M_TXF_READ_THRESHOLD 0xff -#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD) -#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD) - -#define S_TXF_WRITE_THRESHOLD 16 -#define M_TXF_WRITE_THRESHOLD 0xff -#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD) -#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD) - -#define MAC_REG_BASE 0x600 -#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg)) - -#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO) -#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI) -#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR) -#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS) -#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN) -#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY) -#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME) -#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO) -#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI) -#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO) -#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI) -#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT) -#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA) -#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED) -#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES) - -#endif diff --git a/drivers/net/chelsio/gmac.h b/drivers/net/chelsio/gmac.h deleted file mode 100644 index d42337457cf..00000000000 --- a/drivers/net/chelsio/gmac.h +++ /dev/null @@ -1,142 +0,0 @@ -/***************************************************************************** - * * - * File: gmac.h * - * $Revision: 1.6 $ * - * $Date: 2005/06/21 18:29:47 $ * - * Description: * - * Generic MAC functionality. * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#ifndef _CXGB_GMAC_H_ -#define _CXGB_GMAC_H_ - -#include "common.h" - -enum { - MAC_STATS_UPDATE_FAST, - MAC_STATS_UPDATE_FULL -}; - -enum { - MAC_DIRECTION_RX = 1, - MAC_DIRECTION_TX = 2 -}; - -struct cmac_statistics { - /* Transmit */ - u64 TxOctetsOK; - u64 TxOctetsBad; - u64 TxUnicastFramesOK; - u64 TxMulticastFramesOK; - u64 TxBroadcastFramesOK; - u64 TxPauseFrames; - u64 TxFramesWithDeferredXmissions; - u64 TxLateCollisions; - u64 TxTotalCollisions; - u64 TxFramesAbortedDueToXSCollisions; - u64 TxUnderrun; - u64 TxLengthErrors; - u64 TxInternalMACXmitError; - u64 TxFramesWithExcessiveDeferral; - u64 TxFCSErrors; - u64 TxJumboFramesOK; - u64 TxJumboOctetsOK; - - /* Receive */ - u64 RxOctetsOK; - u64 RxOctetsBad; - u64 RxUnicastFramesOK; - u64 RxMulticastFramesOK; - u64 RxBroadcastFramesOK; - u64 RxPauseFrames; - u64 RxFCSErrors; - u64 RxAlignErrors; - u64 RxSymbolErrors; - u64 RxDataErrors; - u64 RxSequenceErrors; - u64 RxRuntErrors; - u64 RxJabberErrors; - u64 RxInternalMACRcvError; - u64 RxInRangeLengthErrors; - u64 RxOutOfRangeLengthField; - u64 RxFrameTooLongErrors; - u64 RxJumboFramesOK; - u64 RxJumboOctetsOK; -}; - -struct cmac_ops { - void (*destroy)(struct cmac *); - int (*reset)(struct cmac *); - int (*interrupt_enable)(struct cmac *); - int (*interrupt_disable)(struct cmac *); - int (*interrupt_clear)(struct cmac *); - int (*interrupt_handler)(struct cmac *); - - int (*enable)(struct cmac *, int); - int (*disable)(struct cmac *, int); - - int (*loopback_enable)(struct cmac *); - int (*loopback_disable)(struct cmac *); - - int (*set_mtu)(struct cmac *, int mtu); - int (*set_rx_mode)(struct cmac *, struct t1_rx_mode *rm); - - int (*set_speed_duplex_fc)(struct cmac *, int speed, int duplex, int fc); - int (*get_speed_duplex_fc)(struct cmac *, int *speed, int *duplex, - int *fc); - - const struct cmac_statistics *(*statistics_update)(struct cmac *, int); - - int (*macaddress_get)(struct cmac *, u8 mac_addr[6]); - int (*macaddress_set)(struct cmac *, u8 mac_addr[6]); -}; - -typedef struct _cmac_instance cmac_instance; - -struct cmac { - struct cmac_statistics stats; - adapter_t *adapter; - const struct cmac_ops *ops; - cmac_instance *instance; -}; - -struct gmac { - unsigned int stats_update_period; - struct cmac *(*create)(adapter_t *adapter, int index); - int (*reset)(adapter_t *); -}; - -extern const struct gmac t1_pm3393_ops; -extern const struct gmac t1_vsc7326_ops; - -#endif /* _CXGB_GMAC_H_ */ diff --git a/drivers/net/chelsio/mv88e1xxx.c b/drivers/net/chelsio/mv88e1xxx.c deleted file mode 100644 index 71018a4fdf1..00000000000 --- a/drivers/net/chelsio/mv88e1xxx.c +++ /dev/null @@ -1,397 +0,0 @@ -/* $Date: 2005/10/24 23:18:13 $ $RCSfile: mv88e1xxx.c,v $ $Revision: 1.49 $ */ -#include "common.h" -#include "mv88e1xxx.h" -#include "cphy.h" -#include "elmer0.h" - -/* MV88E1XXX MDI crossover register values */ -#define CROSSOVER_MDI 0 -#define CROSSOVER_MDIX 1 -#define CROSSOVER_AUTO 3 - -#define INTR_ENABLE_MASK 0x6CA0 - -/* - * Set the bits given by 'bitval' in PHY register 'reg'. - */ -static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval) -{ - u32 val; - - (void) simple_mdio_read(cphy, reg, &val); - (void) simple_mdio_write(cphy, reg, val | bitval); -} - -/* - * Clear the bits given by 'bitval' in PHY register 'reg'. - */ -static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval) -{ - u32 val; - - (void) simple_mdio_read(cphy, reg, &val); - (void) simple_mdio_write(cphy, reg, val & ~bitval); -} - -/* - * NAME: phy_reset - * - * DESC: Reset the given PHY's port. NOTE: This is not a global - * chip reset. - * - * PARAMS: cphy - Pointer to PHY instance data. - * - * RETURN: 0 - Successful reset. - * -1 - Timeout. - */ -static int mv88e1xxx_reset(struct cphy *cphy, int wait) -{ - u32 ctl; - int time_out = 1000; - - mdio_set_bit(cphy, MII_BMCR, BMCR_RESET); - - do { - (void) simple_mdio_read(cphy, MII_BMCR, &ctl); - ctl &= BMCR_RESET; - if (ctl) - udelay(1); - } while (ctl && --time_out); - - return ctl ? -1 : 0; -} - -static int mv88e1xxx_interrupt_enable(struct cphy *cphy) -{ - /* Enable PHY interrupts. */ - (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, - INTR_ENABLE_MASK); - - /* Enable Marvell interrupts through Elmer0. */ - if (t1_is_asic(cphy->adapter)) { - u32 elmer; - - t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); - elmer |= ELMER0_GP_BIT1; - if (is_T2(cphy->adapter)) - elmer |= ELMER0_GP_BIT2 | ELMER0_GP_BIT3 | ELMER0_GP_BIT4; - t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); - } - return 0; -} - -static int mv88e1xxx_interrupt_disable(struct cphy *cphy) -{ - /* Disable all phy interrupts. */ - (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0); - - /* Disable Marvell interrupts through Elmer0. */ - if (t1_is_asic(cphy->adapter)) { - u32 elmer; - - t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); - elmer &= ~ELMER0_GP_BIT1; - if (is_T2(cphy->adapter)) - elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4); - t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); - } - return 0; -} - -static int mv88e1xxx_interrupt_clear(struct cphy *cphy) -{ - u32 elmer; - - /* Clear PHY interrupts by reading the register. */ - (void) simple_mdio_read(cphy, - MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer); - - /* Clear Marvell interrupts through Elmer0. */ - if (t1_is_asic(cphy->adapter)) { - t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); - elmer |= ELMER0_GP_BIT1; - if (is_T2(cphy->adapter)) - elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4; - t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); - } - return 0; -} - -/* - * Set the PHY speed and duplex. This also disables auto-negotiation, except - * for 1Gb/s, where auto-negotiation is mandatory. - */ -static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex) -{ - u32 ctl; - - (void) simple_mdio_read(phy, MII_BMCR, &ctl); - if (speed >= 0) { - ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); - if (speed == SPEED_100) - ctl |= BMCR_SPEED100; - else if (speed == SPEED_1000) - ctl |= BMCR_SPEED1000; - } - if (duplex >= 0) { - ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE); - if (duplex == DUPLEX_FULL) - ctl |= BMCR_FULLDPLX; - } - if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */ - ctl |= BMCR_ANENABLE; - (void) simple_mdio_write(phy, MII_BMCR, ctl); - return 0; -} - -static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover) -{ - u32 data32; - - (void) simple_mdio_read(cphy, - MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32); - data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE); - data32 |= V_PSCR_MDI_XOVER_MODE(crossover); - (void) simple_mdio_write(cphy, - MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32); - return 0; -} - -static int mv88e1xxx_autoneg_enable(struct cphy *cphy) -{ - u32 ctl; - - (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO); - - (void) simple_mdio_read(cphy, MII_BMCR, &ctl); - /* restart autoneg for change to take effect */ - ctl |= BMCR_ANENABLE | BMCR_ANRESTART; - (void) simple_mdio_write(cphy, MII_BMCR, ctl); - return 0; -} - -static int mv88e1xxx_autoneg_disable(struct cphy *cphy) -{ - u32 ctl; - - /* - * Crossover *must* be set to manual in order to disable auto-neg. - * The Alaska FAQs document highlights this point. - */ - (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI); - - /* - * Must include autoneg reset when disabling auto-neg. This - * is described in the Alaska FAQ document. - */ - (void) simple_mdio_read(cphy, MII_BMCR, &ctl); - ctl &= ~BMCR_ANENABLE; - (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART); - return 0; -} - -static int mv88e1xxx_autoneg_restart(struct cphy *cphy) -{ - mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART); - return 0; -} - -static int mv88e1xxx_advertise(struct cphy *phy, unsigned int advertise_map) -{ - u32 val = 0; - - if (advertise_map & - (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { - (void) simple_mdio_read(phy, MII_GBCR, &val); - val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL); - if (advertise_map & ADVERTISED_1000baseT_Half) - val |= GBCR_ADV_1000HALF; - if (advertise_map & ADVERTISED_1000baseT_Full) - val |= GBCR_ADV_1000FULL; - } - (void) simple_mdio_write(phy, MII_GBCR, val); - - val = 1; - if (advertise_map & ADVERTISED_10baseT_Half) - val |= ADVERTISE_10HALF; - if (advertise_map & ADVERTISED_10baseT_Full) - val |= ADVERTISE_10FULL; - if (advertise_map & ADVERTISED_100baseT_Half) - val |= ADVERTISE_100HALF; - if (advertise_map & ADVERTISED_100baseT_Full) - val |= ADVERTISE_100FULL; - if (advertise_map & ADVERTISED_PAUSE) - val |= ADVERTISE_PAUSE; - if (advertise_map & ADVERTISED_ASYM_PAUSE) - val |= ADVERTISE_PAUSE_ASYM; - (void) simple_mdio_write(phy, MII_ADVERTISE, val); - return 0; -} - -static int mv88e1xxx_set_loopback(struct cphy *cphy, int on) -{ - if (on) - mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK); - else - mdio_clear_bit(cphy, MII_BMCR, BMCR_LOOPBACK); - return 0; -} - -static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok, - int *speed, int *duplex, int *fc) -{ - u32 status; - int sp = -1, dplx = -1, pause = 0; - - (void) simple_mdio_read(cphy, - MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status); - if ((status & V_PSSR_STATUS_RESOLVED) != 0) { - if (status & V_PSSR_RX_PAUSE) - pause |= PAUSE_RX; - if (status & V_PSSR_TX_PAUSE) - pause |= PAUSE_TX; - dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; - sp = G_PSSR_SPEED(status); - if (sp == 0) - sp = SPEED_10; - else if (sp == 1) - sp = SPEED_100; - else - sp = SPEED_1000; - } - if (link_ok) - *link_ok = (status & V_PSSR_LINK) != 0; - if (speed) - *speed = sp; - if (duplex) - *duplex = dplx; - if (fc) - *fc = pause; - return 0; -} - -static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable) -{ - u32 val; - - (void) simple_mdio_read(cphy, - MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val); - - /* - * Set the downshift counter to 2 so we try to establish Gb link - * twice before downshifting. - */ - val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT)); - - if (downshift_enable) - val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2); - (void) simple_mdio_write(cphy, - MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val); - return 0; -} - -static int mv88e1xxx_interrupt_handler(struct cphy *cphy) -{ - int cphy_cause = 0; - u32 status; - - /* - * Loop until cause reads zero. Need to handle bouncing interrupts. - */ - while (1) { - u32 cause; - - (void) simple_mdio_read(cphy, - MV88E1XXX_INTERRUPT_STATUS_REGISTER, - &cause); - cause &= INTR_ENABLE_MASK; - if (!cause) - break; - - if (cause & MV88E1XXX_INTR_LINK_CHNG) { - (void) simple_mdio_read(cphy, - MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status); - - if (status & MV88E1XXX_INTR_LINK_CHNG) - cphy->state |= PHY_LINK_UP; - else { - cphy->state &= ~PHY_LINK_UP; - if (cphy->state & PHY_AUTONEG_EN) - cphy->state &= ~PHY_AUTONEG_RDY; - cphy_cause |= cphy_cause_link_change; - } - } - - if (cause & MV88E1XXX_INTR_AUTONEG_DONE) - cphy->state |= PHY_AUTONEG_RDY; - - if ((cphy->state & (PHY_LINK_UP | PHY_AUTONEG_RDY)) == - (PHY_LINK_UP | PHY_AUTONEG_RDY)) - cphy_cause |= cphy_cause_link_change; - } - return cphy_cause; -} - -static void mv88e1xxx_destroy(struct cphy *cphy) -{ - kfree(cphy); -} - -static struct cphy_ops mv88e1xxx_ops = { - .destroy = mv88e1xxx_destroy, - .reset = mv88e1xxx_reset, - .interrupt_enable = mv88e1xxx_interrupt_enable, - .interrupt_disable = mv88e1xxx_interrupt_disable, - .interrupt_clear = mv88e1xxx_interrupt_clear, - .interrupt_handler = mv88e1xxx_interrupt_handler, - .autoneg_enable = mv88e1xxx_autoneg_enable, - .autoneg_disable = mv88e1xxx_autoneg_disable, - .autoneg_restart = mv88e1xxx_autoneg_restart, - .advertise = mv88e1xxx_advertise, - .set_loopback = mv88e1xxx_set_loopback, - .set_speed_duplex = mv88e1xxx_set_speed_duplex, - .get_link_status = mv88e1xxx_get_link_status, -}; - -static struct cphy *mv88e1xxx_phy_create(struct net_device *dev, int phy_addr, - const struct mdio_ops *mdio_ops) -{ - struct adapter *adapter = netdev_priv(dev); - struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL); - - if (!cphy) - return NULL; - - cphy_init(cphy, dev, phy_addr, &mv88e1xxx_ops, mdio_ops); - - /* Configure particular PHY's to run in a different mode. */ - if ((board_info(adapter)->caps & SUPPORTED_TP) && - board_info(adapter)->chip_phy == CHBT_PHY_88E1111) { - /* - * Configure the PHY transmitter as class A to reduce EMI. - */ - (void) simple_mdio_write(cphy, - MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB); - (void) simple_mdio_write(cphy, - MV88E1XXX_EXTENDED_REGISTER, 0x8004); - } - (void) mv88e1xxx_downshift_set(cphy, 1); /* Enable downshift */ - - /* LED */ - if (is_T2(adapter)) { - (void) simple_mdio_write(cphy, - MV88E1XXX_LED_CONTROL_REGISTER, 0x1); - } - - return cphy; -} - -static int mv88e1xxx_phy_reset(adapter_t* adapter) -{ - return 0; -} - -const struct gphy t1_mv88e1xxx_ops = { - .create = mv88e1xxx_phy_create, - .reset = mv88e1xxx_phy_reset -}; diff --git a/drivers/net/chelsio/mv88e1xxx.h b/drivers/net/chelsio/mv88e1xxx.h deleted file mode 100644 index 967cc428635..00000000000 --- a/drivers/net/chelsio/mv88e1xxx.h +++ /dev/null @@ -1,127 +0,0 @@ -/* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */ -#ifndef CHELSIO_MV8E1XXX_H -#define CHELSIO_MV8E1XXX_H - -#ifndef BMCR_SPEED1000 -# define BMCR_SPEED1000 0x40 -#endif - -#ifndef ADVERTISE_PAUSE -# define ADVERTISE_PAUSE 0x400 -#endif -#ifndef ADVERTISE_PAUSE_ASYM -# define ADVERTISE_PAUSE_ASYM 0x800 -#endif - -/* Gigabit MII registers */ -#define MII_GBCR 9 /* 1000Base-T control register */ -#define MII_GBSR 10 /* 1000Base-T status register */ - -/* 1000Base-T control register fields */ -#define GBCR_ADV_1000HALF 0x100 -#define GBCR_ADV_1000FULL 0x200 -#define GBCR_PREFER_MASTER 0x400 -#define GBCR_MANUAL_AS_MASTER 0x800 -#define GBCR_MANUAL_CONFIG_ENABLE 0x1000 - -/* 1000Base-T status register fields */ -#define GBSR_LP_1000HALF 0x400 -#define GBSR_LP_1000FULL 0x800 -#define GBSR_REMOTE_OK 0x1000 -#define GBSR_LOCAL_OK 0x2000 -#define GBSR_LOCAL_MASTER 0x4000 -#define GBSR_MASTER_FAULT 0x8000 - -/* Marvell PHY interrupt status bits. */ -#define MV88E1XXX_INTR_JABBER 0x0001 -#define MV88E1XXX_INTR_POLARITY_CHNG 0x0002 -#define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010 -#define MV88E1XXX_INTR_DOWNSHIFT 0x0020 -#define MV88E1XXX_INTR_MDI_XOVER_CHNG 0x0040 -#define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080 -#define MV88E1XXX_INTR_FALSE_CARRIER 0x0100 -#define MV88E1XXX_INTR_SYMBOL_ERROR 0x0200 -#define MV88E1XXX_INTR_LINK_CHNG 0x0400 -#define MV88E1XXX_INTR_AUTONEG_DONE 0x0800 -#define MV88E1XXX_INTR_PAGE_RECV 0x1000 -#define MV88E1XXX_INTR_DUPLEX_CHNG 0x2000 -#define MV88E1XXX_INTR_SPEED_CHNG 0x4000 -#define MV88E1XXX_INTR_AUTONEG_ERR 0x8000 - -/* Marvell PHY specific registers. */ -#define MV88E1XXX_SPECIFIC_CNTRL_REGISTER 16 -#define MV88E1XXX_SPECIFIC_STATUS_REGISTER 17 -#define MV88E1XXX_INTERRUPT_ENABLE_REGISTER 18 -#define MV88E1XXX_INTERRUPT_STATUS_REGISTER 19 -#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20 -#define MV88E1XXX_RECV_ERR_CNTR_REGISTER 21 -#define MV88E1XXX_RES_REGISTER 22 -#define MV88E1XXX_GLOBAL_STATUS_REGISTER 23 -#define MV88E1XXX_LED_CONTROL_REGISTER 24 -#define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER 25 -#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26 -#define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER 27 -#define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER 28 -#define MV88E1XXX_EXTENDED_ADDR_REGISTER 29 -#define MV88E1XXX_EXTENDED_REGISTER 30 - -/* PHY specific control register fields */ -#define S_PSCR_MDI_XOVER_MODE 5 -#define M_PSCR_MDI_XOVER_MODE 0x3 -#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) -#define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE) - -/* Extended PHY specific control register fields */ -#define S_DOWNSHIFT_ENABLE 8 -#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE) - -#define S_DOWNSHIFT_CNT 9 -#define M_DOWNSHIFT_CNT 0x7 -#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) -#define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT) - -/* PHY specific status register fields */ -#define S_PSSR_JABBER 0 -#define V_PSSR_JABBER (1 << S_PSSR_JABBER) - -#define S_PSSR_POLARITY 1 -#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY) - -#define S_PSSR_RX_PAUSE 2 -#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE) - -#define S_PSSR_TX_PAUSE 3 -#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE) - -#define S_PSSR_ENERGY_DETECT 4 -#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT) - -#define S_PSSR_DOWNSHIFT_STATUS 5 -#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS) - -#define S_PSSR_MDI 6 -#define V_PSSR_MDI (1 << S_PSSR_MDI) - -#define S_PSSR_CABLE_LEN 7 -#define M_PSSR_CABLE_LEN 0x7 -#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) -#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN) - -#define S_PSSR_LINK 10 -#define V_PSSR_LINK (1 << S_PSSR_LINK) - -#define S_PSSR_STATUS_RESOLVED 11 -#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED) - -#define S_PSSR_PAGE_RECEIVED 12 -#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED) - -#define S_PSSR_DUPLEX 13 -#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX) - -#define S_PSSR_SPEED 14 -#define M_PSSR_SPEED 0x3 -#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED) -#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED) - -#endif diff --git a/drivers/net/chelsio/mv88x201x.c b/drivers/net/chelsio/mv88x201x.c deleted file mode 100644 index f7136b2fd1e..00000000000 --- a/drivers/net/chelsio/mv88x201x.c +++ /dev/null @@ -1,260 +0,0 @@ -/***************************************************************************** - * * - * File: mv88x201x.c * - * $Revision: 1.12 $ * - * $Date: 2005/04/15 19:27:14 $ * - * Description: * - * Marvell PHY (mv88x201x) functionality. * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#include "cphy.h" -#include "elmer0.h" - -/* - * The 88x2010 Rev C. requires some link status registers * to be read - * twice in order to get the right values. Future * revisions will fix - * this problem and then this macro * can disappear. - */ -#define MV88x2010_LINK_STATUS_BUGS 1 - -static int led_init(struct cphy *cphy) -{ - /* Setup the LED registers so we can turn on/off. - * Writing these bits maps control to another - * register. mmd(0x1) addr(0x7) - */ - cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8304, 0xdddd); - return 0; -} - -static int led_link(struct cphy *cphy, u32 do_enable) -{ - u32 led = 0; -#define LINK_ENABLE_BIT 0x1 - - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, &led); - - if (do_enable & LINK_ENABLE_BIT) { - led |= LINK_ENABLE_BIT; - cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led); - } else { - led &= ~LINK_ENABLE_BIT; - cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led); - } - return 0; -} - -/* Port Reset */ -static int mv88x201x_reset(struct cphy *cphy, int wait) -{ - /* This can be done through registers. It is not required since - * a full chip reset is used. - */ - return 0; -} - -static int mv88x201x_interrupt_enable(struct cphy *cphy) -{ - /* Enable PHY LASI interrupts. */ - cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, - MDIO_PMA_LASI_LSALARM); - - /* Enable Marvell interrupts through Elmer0. */ - if (t1_is_asic(cphy->adapter)) { - u32 elmer; - - t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); - elmer |= ELMER0_GP_BIT6; - t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); - } - return 0; -} - -static int mv88x201x_interrupt_disable(struct cphy *cphy) -{ - /* Disable PHY LASI interrupts. */ - cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0x0); - - /* Disable Marvell interrupts through Elmer0. */ - if (t1_is_asic(cphy->adapter)) { - u32 elmer; - - t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); - elmer &= ~ELMER0_GP_BIT6; - t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); - } - return 0; -} - -static int mv88x201x_interrupt_clear(struct cphy *cphy) -{ - u32 elmer; - u32 val; - -#ifdef MV88x2010_LINK_STATUS_BUGS - /* Required to read twice before clear takes affect. */ - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val); - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val); - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); - - /* Read this register after the others above it else - * the register doesn't clear correctly. - */ - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); -#endif - - /* Clear link status. */ - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); - /* Clear PHY LASI interrupts. */ - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); - -#ifdef MV88x2010_LINK_STATUS_BUGS - /* Do it again. */ - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val); - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val); -#endif - - /* Clear Marvell interrupts through Elmer0. */ - if (t1_is_asic(cphy->adapter)) { - t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); - elmer |= ELMER0_GP_BIT6; - t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); - } - return 0; -} - -static int mv88x201x_interrupt_handler(struct cphy *cphy) -{ - /* Clear interrupts */ - mv88x201x_interrupt_clear(cphy); - - /* We have only enabled link change interrupts and so - * cphy_cause must be a link change interrupt. - */ - return cphy_cause_link_change; -} - -static int mv88x201x_set_loopback(struct cphy *cphy, int on) -{ - return 0; -} - -static int mv88x201x_get_link_status(struct cphy *cphy, int *link_ok, - int *speed, int *duplex, int *fc) -{ - u32 val = 0; - - if (link_ok) { - /* Read link status. */ - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); - val &= MDIO_STAT1_LSTATUS; - *link_ok = (val == MDIO_STAT1_LSTATUS); - /* Turn on/off Link LED */ - led_link(cphy, *link_ok); - } - if (speed) - *speed = SPEED_10000; - if (duplex) - *duplex = DUPLEX_FULL; - if (fc) - *fc = PAUSE_RX | PAUSE_TX; - return 0; -} - -static void mv88x201x_destroy(struct cphy *cphy) -{ - kfree(cphy); -} - -static struct cphy_ops mv88x201x_ops = { - .destroy = mv88x201x_destroy, - .reset = mv88x201x_reset, - .interrupt_enable = mv88x201x_interrupt_enable, - .interrupt_disable = mv88x201x_interrupt_disable, - .interrupt_clear = mv88x201x_interrupt_clear, - .interrupt_handler = mv88x201x_interrupt_handler, - .get_link_status = mv88x201x_get_link_status, - .set_loopback = mv88x201x_set_loopback, - .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | - MDIO_DEVS_PHYXS | MDIO_DEVS_WIS), -}; - -static struct cphy *mv88x201x_phy_create(struct net_device *dev, int phy_addr, - const struct mdio_ops *mdio_ops) -{ - u32 val; - struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL); - - if (!cphy) - return NULL; - - cphy_init(cphy, dev, phy_addr, &mv88x201x_ops, mdio_ops); - - /* Commands the PHY to enable XFP's clock. */ - cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val); - cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val | 1); - - /* Clear link status. Required because of a bug in the PHY. */ - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT2, &val); - cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val); - - /* Allows for Link,Ack LED turn on/off */ - led_init(cphy); - return cphy; -} - -/* Chip Reset */ -static int mv88x201x_phy_reset(adapter_t *adapter) -{ - u32 val; - - t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val &= ~4; - t1_tpi_write(adapter, A_ELMER0_GPO, val); - msleep(100); - - t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); - msleep(1000); - - /* Now lets enable the Laser. Delay 100us */ - t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val |= 0x8000; - t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(100); - return 0; -} - -const struct gphy t1_mv88x201x_ops = { - .create = mv88x201x_phy_create, - .reset = mv88x201x_phy_reset -}; diff --git a/drivers/net/chelsio/my3126.c b/drivers/net/chelsio/my3126.c deleted file mode 100644 index a683fd3bb62..00000000000 --- a/drivers/net/chelsio/my3126.c +++ /dev/null @@ -1,209 +0,0 @@ -/* $Date: 2005/11/12 02:13:49 $ $RCSfile: my3126.c,v $ $Revision: 1.15 $ */ -#include "cphy.h" -#include "elmer0.h" -#include "suni1x10gexp_regs.h" - -/* Port Reset */ -static int my3126_reset(struct cphy *cphy, int wait) -{ - /* - * This can be done through registers. It is not required since - * a full chip reset is used. - */ - return 0; -} - -static int my3126_interrupt_enable(struct cphy *cphy) -{ - schedule_delayed_work(&cphy->phy_update, HZ/30); - t1_tpi_read(cphy->adapter, A_ELMER0_GPO, &cphy->elmer_gpo); - return 0; -} - -static int my3126_interrupt_disable(struct cphy *cphy) -{ - cancel_delayed_work_sync(&cphy->phy_update); - return 0; -} - -static int my3126_interrupt_clear(struct cphy *cphy) -{ - return 0; -} - -#define OFFSET(REG_ADDR) (REG_ADDR << 2) - -static int my3126_interrupt_handler(struct cphy *cphy) -{ - u32 val; - u16 val16; - u16 status; - u32 act_count; - adapter_t *adapter; - adapter = cphy->adapter; - - if (cphy->count == 50) { - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); - val16 = (u16) val; - status = cphy->bmsr ^ val16; - - if (status & MDIO_STAT1_LSTATUS) - t1_link_changed(adapter, 0); - cphy->bmsr = val16; - - /* We have only enabled link change interrupts so it - must be that - */ - cphy->count = 0; - } - - t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL), - SUNI1x10GEXP_BITMSK_MSTAT_SNAP); - t1_tpi_read(adapter, - OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW), &act_count); - t1_tpi_read(adapter, - OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val); - act_count += val; - - /* Populate elmer_gpo with the register value */ - t1_tpi_read(adapter, A_ELMER0_GPO, &val); - cphy->elmer_gpo = val; - - if ( (val & (1 << 8)) || (val & (1 << 19)) || - (cphy->act_count == act_count) || cphy->act_on ) { - if (is_T2(adapter)) - val |= (1 << 9); - else if (t1_is_T1B(adapter)) - val |= (1 << 20); - cphy->act_on = 0; - } else { - if (is_T2(adapter)) - val &= ~(1 << 9); - else if (t1_is_T1B(adapter)) - val &= ~(1 << 20); - cphy->act_on = 1; - } - - t1_tpi_write(adapter, A_ELMER0_GPO, val); - - cphy->elmer_gpo = val; - cphy->act_count = act_count; - cphy->count++; - - return cphy_cause_link_change; -} - -static void my3216_poll(struct work_struct *work) -{ - struct cphy *cphy = container_of(work, struct cphy, phy_update.work); - - my3126_interrupt_handler(cphy); -} - -static int my3126_set_loopback(struct cphy *cphy, int on) -{ - return 0; -} - -/* To check the activity LED */ -static int my3126_get_link_status(struct cphy *cphy, - int *link_ok, int *speed, int *duplex, int *fc) -{ - u32 val; - u16 val16; - adapter_t *adapter; - - adapter = cphy->adapter; - cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); - val16 = (u16) val; - - /* Populate elmer_gpo with the register value */ - t1_tpi_read(adapter, A_ELMER0_GPO, &val); - cphy->elmer_gpo = val; - - *link_ok = (val16 & MDIO_STAT1_LSTATUS); - - if (*link_ok) { - /* Turn on the LED. */ - if (is_T2(adapter)) - val &= ~(1 << 8); - else if (t1_is_T1B(adapter)) - val &= ~(1 << 19); - } else { - /* Turn off the LED. */ - if (is_T2(adapter)) - val |= (1 << 8); - else if (t1_is_T1B(adapter)) - val |= (1 << 19); - } - - t1_tpi_write(adapter, A_ELMER0_GPO, val); - cphy->elmer_gpo = val; - *speed = SPEED_10000; - *duplex = DUPLEX_FULL; - - /* need to add flow control */ - if (fc) - *fc = PAUSE_RX | PAUSE_TX; - - return 0; -} - -static void my3126_destroy(struct cphy *cphy) -{ - kfree(cphy); -} - -static struct cphy_ops my3126_ops = { - .destroy = my3126_destroy, - .reset = my3126_reset, - .interrupt_enable = my3126_interrupt_enable, - .interrupt_disable = my3126_interrupt_disable, - .interrupt_clear = my3126_interrupt_clear, - .interrupt_handler = my3126_interrupt_handler, - .get_link_status = my3126_get_link_status, - .set_loopback = my3126_set_loopback, - .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | - MDIO_DEVS_PHYXS), -}; - -static struct cphy *my3126_phy_create(struct net_device *dev, - int phy_addr, const struct mdio_ops *mdio_ops) -{ - struct cphy *cphy = kzalloc(sizeof (*cphy), GFP_KERNEL); - - if (!cphy) - return NULL; - - cphy_init(cphy, dev, phy_addr, &my3126_ops, mdio_ops); - INIT_DELAYED_WORK(&cphy->phy_update, my3216_poll); - cphy->bmsr = 0; - - return cphy; -} - -/* Chip Reset */ -static int my3126_phy_reset(adapter_t * adapter) -{ - u32 val; - - t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val &= ~4; - t1_tpi_write(adapter, A_ELMER0_GPO, val); - msleep(100); - - t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); - msleep(1000); - - /* Now lets enable the Laser. Delay 100us */ - t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val |= 0x8000; - t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(100); - return 0; -} - -const struct gphy t1_my3126_ops = { - .create = my3126_phy_create, - .reset = my3126_phy_reset -}; diff --git a/drivers/net/chelsio/pm3393.c b/drivers/net/chelsio/pm3393.c deleted file mode 100644 index 40c7b93abab..00000000000 --- a/drivers/net/chelsio/pm3393.c +++ /dev/null @@ -1,796 +0,0 @@ -/***************************************************************************** - * * - * File: pm3393.c * - * $Revision: 1.16 $ * - * $Date: 2005/05/14 00:59:32 $ * - * Description: * - * PMC/SIERRA (pm3393) MAC-PHY functionality. * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#include "common.h" -#include "regs.h" -#include "gmac.h" -#include "elmer0.h" -#include "suni1x10gexp_regs.h" - -#include <linux/crc32.h> -#include <linux/slab.h> - -#define OFFSET(REG_ADDR) ((REG_ADDR) << 2) - -/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */ -#define MAX_FRAME_SIZE 9600 - -#define IPG 12 -#define TXXG_CONF1_VAL ((IPG << SUNI1x10GEXP_BITOFF_TXXG_IPGT) | \ - SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN | SUNI1x10GEXP_BITMSK_TXXG_CRCEN | \ - SUNI1x10GEXP_BITMSK_TXXG_PADEN) -#define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \ - SUNI1x10GEXP_BITMSK_RXXG_FLCHK | SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP) - -/* Update statistics every 15 minutes */ -#define STATS_TICK_SECS (15 * 60) - -enum { /* RMON registers */ - RxOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW, - RxUnicastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW, - RxMulticastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW, - RxBroadcastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW, - RxPAUSEMACCtrlFramesReceived = SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW, - RxFrameCheckSequenceErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW, - RxFramesLostDueToInternalMACErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW, - RxSymbolErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW, - RxInRangeLengthErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW, - RxFramesTooLongErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW, - RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW, - RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW, - RxUndersizedFrames = SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW, - RxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW, - RxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW, - - TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW, - TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW, - TxTransmitSystemError = SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW, - TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW, - TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW, - TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW, - TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW, - TxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW, - TxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW -}; - -struct _cmac_instance { - u8 enabled; - u8 fc; - u8 mac_addr[6]; -}; - -static int pmread(struct cmac *cmac, u32 reg, u32 * data32) -{ - t1_tpi_read(cmac->adapter, OFFSET(reg), data32); - return 0; -} - -static int pmwrite(struct cmac *cmac, u32 reg, u32 data32) -{ - t1_tpi_write(cmac->adapter, OFFSET(reg), data32); - return 0; -} - -/* Port reset. */ -static int pm3393_reset(struct cmac *cmac) -{ - return 0; -} - -/* - * Enable interrupts for the PM3393 - * - * 1. Enable PM3393 BLOCK interrupts. - * 2. Enable PM3393 Master Interrupt bit(INTE) - * 3. Enable ELMER's PM3393 bit. - * 4. Enable Terminator external interrupt. - */ -static int pm3393_interrupt_enable(struct cmac *cmac) -{ - u32 pl_intr; - - /* PM3393 - Enabling all hardware block interrupts. - */ - pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff); - - /* Don't interrupt on statistics overflow, we are polling */ - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); - - pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff); - - /* PM3393 - Global interrupt enable - */ - /* TBD XXX Disable for now until we figure out why error interrupts keep asserting. */ - pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, - 0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ ); - - /* TERMINATOR - PL_INTERUPTS_EXT */ - pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); - pl_intr |= F_PL_INTR_EXT; - writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); - return 0; -} - -static int pm3393_interrupt_disable(struct cmac *cmac) -{ - u32 elmer; - - /* PM3393 - Enabling HW interrupt blocks. */ - pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0); - pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0); - - /* PM3393 - Global interrupt enable */ - pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0); - - /* ELMER - External chip interrupts. */ - t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer); - elmer &= ~ELMER0_GP_BIT1; - t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); - - /* TERMINATOR - PL_INTERUPTS_EXT */ - /* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP - * COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level. - */ - - return 0; -} - -static int pm3393_interrupt_clear(struct cmac *cmac) -{ - u32 elmer; - u32 pl_intr; - u32 val32; - - /* PM3393 - Clearing HW interrupt blocks. Note, this assumes - * bit WCIMODE=0 for a clear-on-read. - */ - pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32); - pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32); - pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32); - pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32); - pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32); - pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32); - pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32); - pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32); - pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32); - pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32); - pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32); - pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION, - &val32); - pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32); - pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32); - - /* PM3393 - Global interrupt status - */ - pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32); - - /* ELMER - External chip interrupts. - */ - t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer); - elmer |= ELMER0_GP_BIT1; - t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer); - - /* TERMINATOR - PL_INTERUPTS_EXT - */ - pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE); - pl_intr |= F_PL_INTR_EXT; - writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE); - - return 0; -} - -/* Interrupt handler */ -static int pm3393_interrupt_handler(struct cmac *cmac) -{ - u32 master_intr_status; - - /* Read the master interrupt status register. */ - pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, - &master_intr_status); - if (netif_msg_intr(cmac->adapter)) - dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n", - master_intr_status); - - /* TBD XXX Lets just clear everything for now */ - pm3393_interrupt_clear(cmac); - - return 0; -} - -static int pm3393_enable(struct cmac *cmac, int which) -{ - if (which & MAC_DIRECTION_RX) - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, - (RXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_RXXG_RXEN)); - - if (which & MAC_DIRECTION_TX) { - u32 val = TXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_TXXG_TXEN0; - - if (cmac->instance->fc & PAUSE_RX) - val |= SUNI1x10GEXP_BITMSK_TXXG_FCRX; - if (cmac->instance->fc & PAUSE_TX) - val |= SUNI1x10GEXP_BITMSK_TXXG_FCTX; - pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val); - } - - cmac->instance->enabled |= which; - return 0; -} - -static int pm3393_enable_port(struct cmac *cmac, int which) -{ - /* Clear port statistics */ - pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL, - SUNI1x10GEXP_BITMSK_MSTAT_CLEAR); - udelay(2); - memset(&cmac->stats, 0, sizeof(struct cmac_statistics)); - - pm3393_enable(cmac, which); - - /* - * XXX This should be done by the PHY and preferably not at all. - * The PHY doesn't give us link status indication on its own so have - * the link management code query it instead. - */ - t1_link_changed(cmac->adapter, 0); - return 0; -} - -static int pm3393_disable(struct cmac *cmac, int which) -{ - if (which & MAC_DIRECTION_RX) - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL); - if (which & MAC_DIRECTION_TX) - pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL); - - /* - * The disable is graceful. Give the PM3393 time. Can't wait very - * long here, we may be holding locks. - */ - udelay(20); - - cmac->instance->enabled &= ~which; - return 0; -} - -static int pm3393_loopback_enable(struct cmac *cmac) -{ - return 0; -} - -static int pm3393_loopback_disable(struct cmac *cmac) -{ - return 0; -} - -static int pm3393_set_mtu(struct cmac *cmac, int mtu) -{ - int enabled = cmac->instance->enabled; - - /* MAX_FRAME_SIZE includes header + FCS, mtu doesn't */ - mtu += 14 + 4; - if (mtu > MAX_FRAME_SIZE) - return -EINVAL; - - /* Disable Rx/Tx MAC before configuring it. */ - if (enabled) - pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); - - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu); - pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu); - - if (enabled) - pm3393_enable(cmac, enabled); - return 0; -} - -static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm) -{ - int enabled = cmac->instance->enabled & MAC_DIRECTION_RX; - u32 rx_mode; - - /* Disable MAC RX before reconfiguring it */ - if (enabled) - pm3393_disable(cmac, MAC_DIRECTION_RX); - - pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode); - rx_mode &= ~(SUNI1x10GEXP_BITMSK_RXXG_PMODE | - SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, - (u16)rx_mode); - - if (t1_rx_mode_promisc(rm)) { - /* Promiscuous mode. */ - rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_PMODE; - } - if (t1_rx_mode_allmulti(rm)) { - /* Accept all multicast. */ - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff); - rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN; - } else if (t1_rx_mode_mc_cnt(rm)) { - /* Accept one or more multicast(s). */ - struct netdev_hw_addr *ha; - int bit; - u16 mc_filter[4] = { 0, }; - - netdev_for_each_mc_addr(ha, t1_get_netdev(rm)) { - /* bit[23:28] */ - bit = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x3f; - mc_filter[bit >> 4] |= 1 << (bit & 0xf); - } - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]); - rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN; - } - - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode); - - if (enabled) - pm3393_enable(cmac, MAC_DIRECTION_RX); - - return 0; -} - -static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed, - int *duplex, int *fc) -{ - if (speed) - *speed = SPEED_10000; - if (duplex) - *duplex = DUPLEX_FULL; - if (fc) - *fc = cmac->instance->fc; - return 0; -} - -static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex, - int fc) -{ - if (speed >= 0 && speed != SPEED_10000) - return -1; - if (duplex >= 0 && duplex != DUPLEX_FULL) - return -1; - if (fc & ~(PAUSE_TX | PAUSE_RX)) - return -1; - - if (fc != cmac->instance->fc) { - cmac->instance->fc = (u8) fc; - if (cmac->instance->enabled & MAC_DIRECTION_TX) - pm3393_enable(cmac, MAC_DIRECTION_TX); - } - return 0; -} - -#define RMON_UPDATE(mac, name, stat_name) \ -{ \ - t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \ - t1_tpi_read((mac)->adapter, OFFSET((name)+1), &val1); \ - t1_tpi_read((mac)->adapter, OFFSET((name)+2), &val2); \ - (mac)->stats.stat_name = (u64)(val0 & 0xffff) | \ - ((u64)(val1 & 0xffff) << 16) | \ - ((u64)(val2 & 0xff) << 32) | \ - ((mac)->stats.stat_name & \ - 0xffffff0000000000ULL); \ - if (ro & \ - (1ULL << ((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2))) \ - (mac)->stats.stat_name += 1ULL << 40; \ -} - -static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac, - int flag) -{ - u64 ro; - u32 val0, val1, val2, val3; - - /* Snap the counters */ - pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL, - SUNI1x10GEXP_BITMSK_MSTAT_SNAP); - - /* Counter rollover, clear on read */ - pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0); - pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1, &val1); - pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2, &val2); - pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3, &val3); - ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) | - (((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48); - - /* Rx stats */ - RMON_UPDATE(mac, RxOctetsReceivedOK, RxOctetsOK); - RMON_UPDATE(mac, RxUnicastFramesReceivedOK, RxUnicastFramesOK); - RMON_UPDATE(mac, RxMulticastFramesReceivedOK, RxMulticastFramesOK); - RMON_UPDATE(mac, RxBroadcastFramesReceivedOK, RxBroadcastFramesOK); - RMON_UPDATE(mac, RxPAUSEMACCtrlFramesReceived, RxPauseFrames); - RMON_UPDATE(mac, RxFrameCheckSequenceErrors, RxFCSErrors); - RMON_UPDATE(mac, RxFramesLostDueToInternalMACErrors, - RxInternalMACRcvError); - RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors); - RMON_UPDATE(mac, RxInRangeLengthErrors, RxInRangeLengthErrors); - RMON_UPDATE(mac, RxFramesTooLongErrors , RxFrameTooLongErrors); - RMON_UPDATE(mac, RxJabbers, RxJabberErrors); - RMON_UPDATE(mac, RxFragments, RxRuntErrors); - RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors); - RMON_UPDATE(mac, RxJumboFramesReceivedOK, RxJumboFramesOK); - RMON_UPDATE(mac, RxJumboOctetsReceivedOK, RxJumboOctetsOK); - - /* Tx stats */ - RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK); - RMON_UPDATE(mac, TxFramesLostDueToInternalMACTransmissionError, - TxInternalMACXmitError); - RMON_UPDATE(mac, TxTransmitSystemError, TxFCSErrors); - RMON_UPDATE(mac, TxUnicastFramesTransmittedOK, TxUnicastFramesOK); - RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK); - RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK); - RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames); - RMON_UPDATE(mac, TxJumboFramesReceivedOK, TxJumboFramesOK); - RMON_UPDATE(mac, TxJumboOctetsReceivedOK, TxJumboOctetsOK); - - return &mac->stats; -} - -static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6]) -{ - memcpy(mac_addr, cmac->instance->mac_addr, 6); - return 0; -} - -static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6]) -{ - u32 val, lo, mid, hi, enabled = cmac->instance->enabled; - - /* - * MAC addr: 00:07:43:00:13:09 - * - * ma[5] = 0x09 - * ma[4] = 0x13 - * ma[3] = 0x00 - * ma[2] = 0x43 - * ma[1] = 0x07 - * ma[0] = 0x00 - * - * The PM3393 requires byte swapping and reverse order entry - * when programming MAC addresses: - * - * low_bits[15:0] = ma[1]:ma[0] - * mid_bits[31:16] = ma[3]:ma[2] - * high_bits[47:32] = ma[5]:ma[4] - */ - - /* Store local copy */ - memcpy(cmac->instance->mac_addr, ma, 6); - - lo = ((u32) ma[1] << 8) | (u32) ma[0]; - mid = ((u32) ma[3] << 8) | (u32) ma[2]; - hi = ((u32) ma[5] << 8) | (u32) ma[4]; - - /* Disable Rx/Tx MAC before configuring it. */ - if (enabled) - pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); - - /* Set RXXG Station Address */ - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi); - - /* Set TXXG Station Address */ - pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo); - pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid); - pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi); - - /* Setup Exact Match Filter 1 with our MAC address - * - * Must disable exact match filter before configuring it. - */ - pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val); - val &= 0xff0f; - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); - - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid); - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi); - - val |= 0x0090; - pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); - - if (enabled) - pm3393_enable(cmac, enabled); - return 0; -} - -static void pm3393_destroy(struct cmac *cmac) -{ - kfree(cmac); -} - -static struct cmac_ops pm3393_ops = { - .destroy = pm3393_destroy, - .reset = pm3393_reset, - .interrupt_enable = pm3393_interrupt_enable, - .interrupt_disable = pm3393_interrupt_disable, - .interrupt_clear = pm3393_interrupt_clear, - .interrupt_handler = pm3393_interrupt_handler, - .enable = pm3393_enable_port, - .disable = pm3393_disable, - .loopback_enable = pm3393_loopback_enable, - .loopback_disable = pm3393_loopback_disable, - .set_mtu = pm3393_set_mtu, - .set_rx_mode = pm3393_set_rx_mode, - .get_speed_duplex_fc = pm3393_get_speed_duplex_fc, - .set_speed_duplex_fc = pm3393_set_speed_duplex_fc, - .statistics_update = pm3393_update_statistics, - .macaddress_get = pm3393_macaddress_get, - .macaddress_set = pm3393_macaddress_set -}; - -static struct cmac *pm3393_mac_create(adapter_t *adapter, int index) -{ - struct cmac *cmac; - - cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL); - if (!cmac) - return NULL; - - cmac->ops = &pm3393_ops; - cmac->instance = (cmac_instance *) (cmac + 1); - cmac->adapter = adapter; - cmac->instance->fc = PAUSE_TX | PAUSE_RX; - - t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000); - t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000); - t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800); - t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */ - t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800); - t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00); - t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */ - - t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */ - t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */ - t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */ - t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */ - t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */ - t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */ - t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */ - t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */ - t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */ - t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */ - t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */ - t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit are undocumented */ - t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */ - - t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */ - t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */ - t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */ - t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */ - t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */ - t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */ - t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */ - t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */ - t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */ - t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */ - t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other bit are undocumented */ - - t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */ - t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */ - t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */ - t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */ - t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */ - t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */ - - t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */ - t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */ - - t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */ - t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */ - - t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */ - /* For T1 use timer based Mac flow control. */ - t1_tpi_write(adapter, OFFSET(0x304d), 0x8000); - t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */ - t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */ - t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */ - - /* Setup Exact Match Filter 0 to allow broadcast packets. - */ - t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */ - t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */ - t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */ - t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */ - t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */ - - t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */ - t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */ - t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */ - - return cmac; -} - -static int pm3393_mac_reset(adapter_t * adapter) -{ - u32 val; - u32 x; - u32 is_pl4_reset_finished; - u32 is_pl4_outof_lock; - u32 is_xaui_mabc_pll_locked; - u32 successful_reset; - int i; - - /* The following steps are required to properly reset - * the PM3393. This information is provided in the - * PM3393 datasheet (Issue 2: November 2002) - * section 13.1 -- Device Reset. - * - * The PM3393 has three types of components that are - * individually reset: - * - * DRESETB - Digital circuitry - * PL4_ARESETB - PL4 analog circuitry - * XAUI_ARESETB - XAUI bus analog circuitry - * - * Steps to reset PM3393 using RSTB pin: - * - * 1. Assert RSTB pin low ( write 0 ) - * 2. Wait at least 1ms to initiate a complete initialization of device. - * 3. Wait until all external clocks and REFSEL are stable. - * 4. Wait minimum of 1ms. (after external clocks and REFEL are stable) - * 5. De-assert RSTB ( write 1 ) - * 6. Wait until internal timers to expires after ~14ms. - * - Allows analog clock synthesizer(PL4CSU) to stabilize to - * selected reference frequency before allowing the digital - * portion of the device to operate. - * 7. Wait at least 200us for XAUI interface to stabilize. - * 8. Verify the PM3393 came out of reset successfully. - * Set successful reset flag if everything worked else try again - * a few more times. - */ - - successful_reset = 0; - for (i = 0; i < 3 && !successful_reset; i++) { - /* 1 */ - t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val &= ~1; - t1_tpi_write(adapter, A_ELMER0_GPO, val); - - /* 2 */ - msleep(1); - - /* 3 */ - msleep(1); - - /* 4 */ - msleep(2 /*1 extra ms for safety */ ); - - /* 5 */ - val |= 1; - t1_tpi_write(adapter, A_ELMER0_GPO, val); - - /* 6 */ - msleep(15 /*1 extra ms for safety */ ); - - /* 7 */ - msleep(1); - - /* 8 */ - - /* Has PL4 analog block come out of reset correctly? */ - t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val); - is_pl4_reset_finished = (val & SUNI1x10GEXP_BITMSK_TOP_EXPIRED); - - /* TBD XXX SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL gets locked later in the init sequence - * figure out why? */ - - /* Have all PL4 block clocks locked? */ - x = (SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL - /*| SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL */ | - SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL | - SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL | - SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL); - is_pl4_outof_lock = (val & x); - - /* ??? If this fails, might be able to software reset the XAUI part - * and try to recover... thus saving us from doing another HW reset */ - /* Has the XAUI MABC PLL circuitry stablized? */ - is_xaui_mabc_pll_locked = - (val & SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED); - - successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock - && is_xaui_mabc_pll_locked); - - if (netif_msg_hw(adapter)) - dev_dbg(&adapter->pdev->dev, - "PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, " - "is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n", - i, is_pl4_reset_finished, val, - is_pl4_outof_lock, is_xaui_mabc_pll_locked); - } - return successful_reset ? 0 : 1; -} - -const struct gmac t1_pm3393_ops = { - .stats_update_period = STATS_TICK_SECS, - .create = pm3393_mac_create, - .reset = pm3393_mac_reset, -}; diff --git a/drivers/net/chelsio/regs.h b/drivers/net/chelsio/regs.h deleted file mode 100644 index c80bf4d6d0a..00000000000 --- a/drivers/net/chelsio/regs.h +++ /dev/null @@ -1,2168 +0,0 @@ -/***************************************************************************** - * * - * File: regs.h * - * $Revision: 1.8 $ * - * $Date: 2005/06/21 18:29:48 $ * - * Description: * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#ifndef _CXGB_REGS_H_ -#define _CXGB_REGS_H_ - -/* SGE registers */ -#define A_SG_CONTROL 0x0 - -#define S_CMDQ0_ENABLE 0 -#define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) -#define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U) - -#define S_CMDQ1_ENABLE 1 -#define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) -#define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U) - -#define S_FL0_ENABLE 2 -#define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) -#define F_FL0_ENABLE V_FL0_ENABLE(1U) - -#define S_FL1_ENABLE 3 -#define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) -#define F_FL1_ENABLE V_FL1_ENABLE(1U) - -#define S_CPL_ENABLE 4 -#define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) -#define F_CPL_ENABLE V_CPL_ENABLE(1U) - -#define S_RESPONSE_QUEUE_ENABLE 5 -#define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) -#define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U) - -#define S_CMDQ_PRIORITY 6 -#define M_CMDQ_PRIORITY 0x3 -#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) -#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) - -#define S_DISABLE_CMDQ0_GTS 8 -#define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) -#define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U) - -#define S_DISABLE_CMDQ1_GTS 9 -#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) -#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U) - -#define S_DISABLE_FL0_GTS 10 -#define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS) -#define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U) - -#define S_DISABLE_FL1_GTS 11 -#define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS) -#define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U) - -#define S_ENABLE_BIG_ENDIAN 12 -#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN) -#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U) - -#define S_FL_SELECTION_CRITERIA 13 -#define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA) -#define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U) - -#define S_ISCSI_COALESCE 14 -#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE) -#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U) - -#define S_RX_PKT_OFFSET 15 -#define M_RX_PKT_OFFSET 0x7 -#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET) -#define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET) - -#define S_VLAN_XTRACT 18 -#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT) -#define F_VLAN_XTRACT V_VLAN_XTRACT(1U) - -#define A_SG_DOORBELL 0x4 -#define A_SG_CMD0BASELWR 0x8 -#define A_SG_CMD0BASEUPR 0xc -#define A_SG_CMD1BASELWR 0x10 -#define A_SG_CMD1BASEUPR 0x14 -#define A_SG_FL0BASELWR 0x18 -#define A_SG_FL0BASEUPR 0x1c -#define A_SG_FL1BASELWR 0x20 -#define A_SG_FL1BASEUPR 0x24 -#define A_SG_CMD0SIZE 0x28 - -#define S_CMDQ0_SIZE 0 -#define M_CMDQ0_SIZE 0x1ffff -#define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE) -#define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE) - -#define A_SG_FL0SIZE 0x2c - -#define S_FL0_SIZE 0 -#define M_FL0_SIZE 0x1ffff -#define V_FL0_SIZE(x) ((x) << S_FL0_SIZE) -#define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE) - -#define A_SG_RSPSIZE 0x30 - -#define S_RESPQ_SIZE 0 -#define M_RESPQ_SIZE 0x1ffff -#define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE) -#define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE) - -#define A_SG_RSPBASELWR 0x34 -#define A_SG_RSPBASEUPR 0x38 -#define A_SG_FLTHRESHOLD 0x3c - -#define S_FL_THRESHOLD 0 -#define M_FL_THRESHOLD 0xffff -#define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD) -#define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD) - -#define A_SG_RSPQUEUECREDIT 0x40 - -#define S_RESPQ_CREDIT 0 -#define M_RESPQ_CREDIT 0x1ffff -#define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT) -#define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT) - -#define A_SG_SLEEPING 0x48 - -#define S_SLEEPING 0 -#define M_SLEEPING 0xffff -#define V_SLEEPING(x) ((x) << S_SLEEPING) -#define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING) - -#define A_SG_INTRTIMER 0x4c - -#define S_INTERRUPT_TIMER_COUNT 0 -#define M_INTERRUPT_TIMER_COUNT 0xffffff -#define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT) -#define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT) - -#define A_SG_CMD0PTR 0x50 - -#define S_CMDQ0_POINTER 0 -#define M_CMDQ0_POINTER 0xffff -#define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER) -#define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER) - -#define S_CURRENT_GENERATION_BIT 16 -#define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT) -#define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U) - -#define A_SG_CMD1PTR 0x54 - -#define S_CMDQ1_POINTER 0 -#define M_CMDQ1_POINTER 0xffff -#define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER) -#define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER) - -#define A_SG_FL0PTR 0x58 - -#define S_FL0_POINTER 0 -#define M_FL0_POINTER 0xffff -#define V_FL0_POINTER(x) ((x) << S_FL0_POINTER) -#define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER) - -#define A_SG_FL1PTR 0x5c - -#define S_FL1_POINTER 0 -#define M_FL1_POINTER 0xffff -#define V_FL1_POINTER(x) ((x) << S_FL1_POINTER) -#define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER) - -#define A_SG_VERSION 0x6c - -#define S_DAY 0 -#define M_DAY 0x1f -#define V_DAY(x) ((x) << S_DAY) -#define G_DAY(x) (((x) >> S_DAY) & M_DAY) - -#define S_MONTH 5 -#define M_MONTH 0xf -#define V_MONTH(x) ((x) << S_MONTH) -#define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH) - -#define A_SG_CMD1SIZE 0xb0 - -#define S_CMDQ1_SIZE 0 -#define M_CMDQ1_SIZE 0x1ffff -#define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE) -#define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE) - -#define A_SG_FL1SIZE 0xb4 - -#define S_FL1_SIZE 0 -#define M_FL1_SIZE 0x1ffff -#define V_FL1_SIZE(x) ((x) << S_FL1_SIZE) -#define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE) - -#define A_SG_INT_ENABLE 0xb8 - -#define S_RESPQ_EXHAUSTED 0 -#define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED) -#define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U) - -#define S_RESPQ_OVERFLOW 1 -#define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW) -#define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U) - -#define S_FL_EXHAUSTED 2 -#define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED) -#define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U) - -#define S_PACKET_TOO_BIG 3 -#define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG) -#define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U) - -#define S_PACKET_MISMATCH 4 -#define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH) -#define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U) - -#define A_SG_INT_CAUSE 0xbc -#define A_SG_RESPACCUTIMER 0xc0 - -/* MC3 registers */ -#define A_MC3_CFG 0x100 - -#define S_CLK_ENABLE 0 -#define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE) -#define F_CLK_ENABLE V_CLK_ENABLE(1U) - -#define S_READY 1 -#define V_READY(x) ((x) << S_READY) -#define F_READY V_READY(1U) - -#define S_READ_TO_WRITE_DELAY 2 -#define M_READ_TO_WRITE_DELAY 0x7 -#define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY) -#define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY) - -#define S_WRITE_TO_READ_DELAY 5 -#define M_WRITE_TO_READ_DELAY 0x7 -#define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY) -#define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY) - -#define S_MC3_BANK_CYCLE 8 -#define M_MC3_BANK_CYCLE 0xf -#define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE) -#define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE) - -#define S_REFRESH_CYCLE 12 -#define M_REFRESH_CYCLE 0xf -#define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE) -#define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE) - -#define S_PRECHARGE_CYCLE 16 -#define M_PRECHARGE_CYCLE 0x3 -#define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE) -#define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE) - -#define S_ACTIVE_TO_READ_WRITE_DELAY 18 -#define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY) -#define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U) - -#define S_ACTIVE_TO_PRECHARGE_DELAY 19 -#define M_ACTIVE_TO_PRECHARGE_DELAY 0x7 -#define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY) -#define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY) - -#define S_WRITE_RECOVERY_DELAY 22 -#define M_WRITE_RECOVERY_DELAY 0x3 -#define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY) -#define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY) - -#define S_DENSITY 24 -#define M_DENSITY 0x3 -#define V_DENSITY(x) ((x) << S_DENSITY) -#define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY) - -#define S_ORGANIZATION 26 -#define V_ORGANIZATION(x) ((x) << S_ORGANIZATION) -#define F_ORGANIZATION V_ORGANIZATION(1U) - -#define S_BANKS 27 -#define V_BANKS(x) ((x) << S_BANKS) -#define F_BANKS V_BANKS(1U) - -#define S_UNREGISTERED 28 -#define V_UNREGISTERED(x) ((x) << S_UNREGISTERED) -#define F_UNREGISTERED V_UNREGISTERED(1U) - -#define S_MC3_WIDTH 29 -#define M_MC3_WIDTH 0x3 -#define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH) -#define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH) - -#define S_MC3_SLOW 31 -#define V_MC3_SLOW(x) ((x) << S_MC3_SLOW) -#define F_MC3_SLOW V_MC3_SLOW(1U) - -#define A_MC3_MODE 0x104 - -#define S_MC3_MODE 0 -#define M_MC3_MODE 0x3fff -#define V_MC3_MODE(x) ((x) << S_MC3_MODE) -#define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE) - -#define S_BUSY 31 -#define V_BUSY(x) ((x) << S_BUSY) -#define F_BUSY V_BUSY(1U) - -#define A_MC3_EXT_MODE 0x108 - -#define S_MC3_EXTENDED_MODE 0 -#define M_MC3_EXTENDED_MODE 0x3fff -#define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE) -#define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE) - -#define A_MC3_PRECHARG 0x10c -#define A_MC3_REFRESH 0x110 - -#define S_REFRESH_ENABLE 0 -#define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE) -#define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U) - -#define S_REFRESH_DIVISOR 1 -#define M_REFRESH_DIVISOR 0x3fff -#define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR) -#define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR) - -#define A_MC3_STROBE 0x114 - -#define S_MASTER_DLL_RESET 0 -#define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET) -#define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U) - -#define S_MASTER_DLL_TAP_COUNT 1 -#define M_MASTER_DLL_TAP_COUNT 0xff -#define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT) -#define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT) - -#define S_MASTER_DLL_LOCKED 9 -#define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED) -#define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U) - -#define S_MASTER_DLL_MAX_TAP_COUNT 10 -#define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT) -#define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U) - -#define S_MASTER_DLL_TAP_COUNT_OFFSET 11 -#define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f -#define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET) -#define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET) - -#define S_SLAVE_DLL_RESET 11 -#define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET) -#define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U) - -#define S_SLAVE_DLL_DELTA 12 -#define M_SLAVE_DLL_DELTA 0xf -#define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA) -#define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA) - -#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17 -#define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f -#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) -#define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) - -#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23 -#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE) -#define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U) - -#define S_SLAVE_DELAY_LINE_TAP_COUNT 24 -#define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f -#define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT) -#define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT) - -#define A_MC3_ECC_CNTL 0x118 - -#define S_ECC_GENERATION_ENABLE 0 -#define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE) -#define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U) - -#define S_ECC_CHECK_ENABLE 1 -#define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE) -#define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U) - -#define S_CORRECTABLE_ERROR_COUNT 2 -#define M_CORRECTABLE_ERROR_COUNT 0xff -#define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT) -#define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT) - -#define S_UNCORRECTABLE_ERROR_COUNT 10 -#define M_UNCORRECTABLE_ERROR_COUNT 0xff -#define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT) -#define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT) - -#define A_MC3_CE_ADDR 0x11c - -#define S_MC3_CE_ADDR 4 -#define M_MC3_CE_ADDR 0xfffffff -#define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR) -#define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR) - -#define A_MC3_CE_DATA0 0x120 -#define A_MC3_CE_DATA1 0x124 -#define A_MC3_CE_DATA2 0x128 -#define A_MC3_CE_DATA3 0x12c -#define A_MC3_CE_DATA4 0x130 -#define A_MC3_UE_ADDR 0x134 - -#define S_MC3_UE_ADDR 4 -#define M_MC3_UE_ADDR 0xfffffff -#define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR) -#define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR) - -#define A_MC3_UE_DATA0 0x138 -#define A_MC3_UE_DATA1 0x13c -#define A_MC3_UE_DATA2 0x140 -#define A_MC3_UE_DATA3 0x144 -#define A_MC3_UE_DATA4 0x148 -#define A_MC3_BD_ADDR 0x14c -#define A_MC3_BD_DATA0 0x150 -#define A_MC3_BD_DATA1 0x154 -#define A_MC3_BD_DATA2 0x158 -#define A_MC3_BD_DATA3 0x15c -#define A_MC3_BD_DATA4 0x160 -#define A_MC3_BD_OP 0x164 - -#define S_BACK_DOOR_OPERATION 0 -#define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION) -#define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U) - -#define A_MC3_BIST_ADDR_BEG 0x168 -#define A_MC3_BIST_ADDR_END 0x16c -#define A_MC3_BIST_DATA 0x170 -#define A_MC3_BIST_OP 0x174 - -#define S_OP 0 -#define V_OP(x) ((x) << S_OP) -#define F_OP V_OP(1U) - -#define S_DATA_PATTERN 1 -#define M_DATA_PATTERN 0x3 -#define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN) -#define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN) - -#define S_CONTINUOUS 3 -#define V_CONTINUOUS(x) ((x) << S_CONTINUOUS) -#define F_CONTINUOUS V_CONTINUOUS(1U) - -#define A_MC3_INT_ENABLE 0x178 - -#define S_MC3_CORR_ERR 0 -#define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR) -#define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U) - -#define S_MC3_UNCORR_ERR 1 -#define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR) -#define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U) - -#define S_MC3_PARITY_ERR 2 -#define M_MC3_PARITY_ERR 0xff -#define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR) -#define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR) - -#define S_MC3_ADDR_ERR 10 -#define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR) -#define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U) - -#define A_MC3_INT_CAUSE 0x17c - -/* MC4 registers */ -#define A_MC4_CFG 0x180 - -#define S_POWER_UP 0 -#define V_POWER_UP(x) ((x) << S_POWER_UP) -#define F_POWER_UP V_POWER_UP(1U) - -#define S_MC4_BANK_CYCLE 8 -#define M_MC4_BANK_CYCLE 0x7 -#define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE) -#define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE) - -#define S_MC4_NARROW 24 -#define V_MC4_NARROW(x) ((x) << S_MC4_NARROW) -#define F_MC4_NARROW V_MC4_NARROW(1U) - -#define S_MC4_SLOW 25 -#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW) -#define F_MC4_SLOW V_MC4_SLOW(1U) - -#define S_MC4A_WIDTH 24 -#define M_MC4A_WIDTH 0x3 -#define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH) -#define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH) - -#define S_MC4A_SLOW 26 -#define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW) -#define F_MC4A_SLOW V_MC4A_SLOW(1U) - -#define A_MC4_MODE 0x184 - -#define S_MC4_MODE 0 -#define M_MC4_MODE 0x7fff -#define V_MC4_MODE(x) ((x) << S_MC4_MODE) -#define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE) - -#define A_MC4_EXT_MODE 0x188 - -#define S_MC4_EXTENDED_MODE 0 -#define M_MC4_EXTENDED_MODE 0x7fff -#define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE) -#define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE) - -#define A_MC4_REFRESH 0x190 -#define A_MC4_STROBE 0x194 -#define A_MC4_ECC_CNTL 0x198 -#define A_MC4_CE_ADDR 0x19c - -#define S_MC4_CE_ADDR 4 -#define M_MC4_CE_ADDR 0xffffff -#define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR) -#define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR) - -#define A_MC4_CE_DATA0 0x1a0 -#define A_MC4_CE_DATA1 0x1a4 -#define A_MC4_CE_DATA2 0x1a8 -#define A_MC4_CE_DATA3 0x1ac -#define A_MC4_CE_DATA4 0x1b0 -#define A_MC4_UE_ADDR 0x1b4 - -#define S_MC4_UE_ADDR 4 -#define M_MC4_UE_ADDR 0xffffff -#define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR) -#define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR) - -#define A_MC4_UE_DATA0 0x1b8 -#define A_MC4_UE_DATA1 0x1bc -#define A_MC4_UE_DATA2 0x1c0 -#define A_MC4_UE_DATA3 0x1c4 -#define A_MC4_UE_DATA4 0x1c8 -#define A_MC4_BD_ADDR 0x1cc - -#define S_MC4_BACK_DOOR_ADDR 0 -#define M_MC4_BACK_DOOR_ADDR 0xfffffff -#define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR) -#define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR) - -#define A_MC4_BD_DATA0 0x1d0 -#define A_MC4_BD_DATA1 0x1d4 -#define A_MC4_BD_DATA2 0x1d8 -#define A_MC4_BD_DATA3 0x1dc -#define A_MC4_BD_DATA4 0x1e0 -#define A_MC4_BD_OP 0x1e4 - -#define S_OPERATION 0 -#define V_OPERATION(x) ((x) << S_OPERATION) -#define F_OPERATION V_OPERATION(1U) - -#define A_MC4_BIST_ADDR_BEG 0x1e8 -#define A_MC4_BIST_ADDR_END 0x1ec -#define A_MC4_BIST_DATA 0x1f0 -#define A_MC4_BIST_OP 0x1f4 -#define A_MC4_INT_ENABLE 0x1f8 - -#define S_MC4_CORR_ERR 0 -#define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR) -#define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U) - -#define S_MC4_UNCORR_ERR 1 -#define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR) -#define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U) - -#define S_MC4_ADDR_ERR 2 -#define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR) -#define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U) - -#define A_MC4_INT_CAUSE 0x1fc - -/* TPI registers */ -#define A_TPI_ADDR 0x280 - -#define S_TPI_ADDRESS 0 -#define M_TPI_ADDRESS 0xffffff -#define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS) -#define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS) - -#define A_TPI_WR_DATA 0x284 -#define A_TPI_RD_DATA 0x288 -#define A_TPI_CSR 0x28c - -#define S_TPIWR 0 -#define V_TPIWR(x) ((x) << S_TPIWR) -#define F_TPIWR V_TPIWR(1U) - -#define S_TPIRDY 1 -#define V_TPIRDY(x) ((x) << S_TPIRDY) -#define F_TPIRDY V_TPIRDY(1U) - -#define S_INT_DIR 31 -#define V_INT_DIR(x) ((x) << S_INT_DIR) -#define F_INT_DIR V_INT_DIR(1U) - -#define A_TPI_PAR 0x29c - -#define S_TPIPAR 0 -#define M_TPIPAR 0x7f -#define V_TPIPAR(x) ((x) << S_TPIPAR) -#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR) - - -/* TP registers */ -#define A_TP_IN_CONFIG 0x300 - -#define S_TP_IN_CSPI_TUNNEL 0 -#define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL) -#define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U) - -#define S_TP_IN_CSPI_ETHERNET 1 -#define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET) -#define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U) - -#define S_TP_IN_CSPI_CPL 3 -#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL) -#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U) - -#define S_TP_IN_CSPI_POS 4 -#define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS) -#define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U) - -#define S_TP_IN_CSPI_CHECK_IP_CSUM 5 -#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM) -#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U) - -#define S_TP_IN_CSPI_CHECK_TCP_CSUM 6 -#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM) -#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U) - -#define S_TP_IN_ESPI_TUNNEL 7 -#define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL) -#define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U) - -#define S_TP_IN_ESPI_ETHERNET 8 -#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET) -#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U) - -#define S_TP_IN_ESPI_CPL 10 -#define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL) -#define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U) - -#define S_TP_IN_ESPI_POS 11 -#define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS) -#define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U) - -#define S_TP_IN_ESPI_CHECK_IP_CSUM 12 -#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM) -#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U) - -#define S_TP_IN_ESPI_CHECK_TCP_CSUM 13 -#define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM) -#define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U) - -#define S_OFFLOAD_DISABLE 14 -#define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE) -#define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U) - -#define A_TP_OUT_CONFIG 0x304 - -#define S_TP_OUT_C_ETH 0 -#define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH) -#define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U) - -#define S_TP_OUT_CSPI_CPL 2 -#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL) -#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U) - -#define S_TP_OUT_CSPI_POS 3 -#define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS) -#define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U) - -#define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4 -#define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM) -#define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U) - -#define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5 -#define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM) -#define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U) - -#define S_TP_OUT_ESPI_ETHERNET 6 -#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET) -#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U) - -#define S_TP_OUT_ESPI_TAG_ETHERNET 7 -#define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET) -#define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U) - -#define S_TP_OUT_ESPI_CPL 8 -#define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL) -#define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U) - -#define S_TP_OUT_ESPI_POS 9 -#define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS) -#define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U) - -#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10 -#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM) -#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U) - -#define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11 -#define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM) -#define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U) - -#define A_TP_GLOBAL_CONFIG 0x308 - -#define S_IP_TTL 0 -#define M_IP_TTL 0xff -#define V_IP_TTL(x) ((x) << S_IP_TTL) -#define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL) - -#define S_TCAM_SERVER_REGION_USAGE 8 -#define M_TCAM_SERVER_REGION_USAGE 0x3 -#define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE) -#define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE) - -#define S_QOS_MAPPING 10 -#define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING) -#define F_QOS_MAPPING V_QOS_MAPPING(1U) - -#define S_TCP_CSUM 11 -#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM) -#define F_TCP_CSUM V_TCP_CSUM(1U) - -#define S_UDP_CSUM 12 -#define V_UDP_CSUM(x) ((x) << S_UDP_CSUM) -#define F_UDP_CSUM V_UDP_CSUM(1U) - -#define S_IP_CSUM 13 -#define V_IP_CSUM(x) ((x) << S_IP_CSUM) -#define F_IP_CSUM V_IP_CSUM(1U) - -#define S_IP_ID_SPLIT 14 -#define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT) -#define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U) - -#define S_PATH_MTU 15 -#define V_PATH_MTU(x) ((x) << S_PATH_MTU) -#define F_PATH_MTU V_PATH_MTU(1U) - -#define S_5TUPLE_LOOKUP 17 -#define M_5TUPLE_LOOKUP 0x3 -#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP) -#define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP) - -#define S_IP_FRAGMENT_DROP 19 -#define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP) -#define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U) - -#define S_PING_DROP 20 -#define V_PING_DROP(x) ((x) << S_PING_DROP) -#define F_PING_DROP V_PING_DROP(1U) - -#define S_PROTECT_MODE 21 -#define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE) -#define F_PROTECT_MODE V_PROTECT_MODE(1U) - -#define S_SYN_COOKIE_ALGORITHM 22 -#define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM) -#define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U) - -#define S_ATTACK_FILTER 23 -#define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER) -#define F_ATTACK_FILTER V_ATTACK_FILTER(1U) - -#define S_INTERFACE_TYPE 24 -#define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE) -#define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U) - -#define S_DISABLE_RX_FLOW_CONTROL 25 -#define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL) -#define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U) - -#define S_SYN_COOKIE_PARAMETER 26 -#define M_SYN_COOKIE_PARAMETER 0x3f -#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER) -#define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER) - -#define A_TP_GLOBAL_RX_CREDITS 0x30c -#define A_TP_CM_SIZE 0x310 -#define A_TP_CM_MM_BASE 0x314 - -#define S_CM_MEMMGR_BASE 0 -#define M_CM_MEMMGR_BASE 0xfffffff -#define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE) -#define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE) - -#define A_TP_CM_TIMER_BASE 0x318 - -#define S_CM_TIMER_BASE 0 -#define M_CM_TIMER_BASE 0xfffffff -#define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE) -#define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE) - -#define A_TP_PM_SIZE 0x31c -#define A_TP_PM_TX_BASE 0x320 -#define A_TP_PM_DEFRAG_BASE 0x324 -#define A_TP_PM_RX_BASE 0x328 -#define A_TP_PM_RX_PG_SIZE 0x32c -#define A_TP_PM_RX_MAX_PGS 0x330 -#define A_TP_PM_TX_PG_SIZE 0x334 -#define A_TP_PM_TX_MAX_PGS 0x338 -#define A_TP_TCP_OPTIONS 0x340 - -#define S_TIMESTAMP 0 -#define M_TIMESTAMP 0x3 -#define V_TIMESTAMP(x) ((x) << S_TIMESTAMP) -#define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP) - -#define S_WINDOW_SCALE 2 -#define M_WINDOW_SCALE 0x3 -#define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE) -#define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE) - -#define S_SACK 4 -#define M_SACK 0x3 -#define V_SACK(x) ((x) << S_SACK) -#define G_SACK(x) (((x) >> S_SACK) & M_SACK) - -#define S_ECN 6 -#define M_ECN 0x3 -#define V_ECN(x) ((x) << S_ECN) -#define G_ECN(x) (((x) >> S_ECN) & M_ECN) - -#define S_SACK_ALGORITHM 8 -#define M_SACK_ALGORITHM 0x3 -#define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM) -#define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM) - -#define S_MSS 10 -#define V_MSS(x) ((x) << S_MSS) -#define F_MSS V_MSS(1U) - -#define S_DEFAULT_PEER_MSS 16 -#define M_DEFAULT_PEER_MSS 0xffff -#define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS) -#define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS) - -#define A_TP_DACK_CONFIG 0x344 - -#define S_DACK_MODE 0 -#define V_DACK_MODE(x) ((x) << S_DACK_MODE) -#define F_DACK_MODE V_DACK_MODE(1U) - -#define S_DACK_AUTO_MGMT 1 -#define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT) -#define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U) - -#define S_DACK_AUTO_CAREFUL 2 -#define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL) -#define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U) - -#define S_DACK_MSS_SELECTOR 3 -#define M_DACK_MSS_SELECTOR 0x3 -#define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR) -#define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR) - -#define S_DACK_BYTE_THRESHOLD 5 -#define M_DACK_BYTE_THRESHOLD 0xfffff -#define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD) -#define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD) - -#define A_TP_PC_CONFIG 0x348 - -#define S_TP_ACCESS_LATENCY 0 -#define M_TP_ACCESS_LATENCY 0xf -#define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY) -#define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY) - -#define S_HELD_FIN_DISABLE 4 -#define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE) -#define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U) - -#define S_DDP_FC_ENABLE 5 -#define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE) -#define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U) - -#define S_RDMA_ERR_ENABLE 6 -#define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE) -#define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U) - -#define S_FAST_PDU_DELIVERY 7 -#define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY) -#define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U) - -#define S_CLEAR_FIN 8 -#define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN) -#define F_CLEAR_FIN V_CLEAR_FIN(1U) - -#define S_DIS_TX_FILL_WIN_PUSH 12 -#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH) -#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U) - -#define S_TP_PC_REV 30 -#define M_TP_PC_REV 0x3 -#define V_TP_PC_REV(x) ((x) << S_TP_PC_REV) -#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV) - -#define A_TP_BACKOFF0 0x350 - -#define S_ELEMENT0 0 -#define M_ELEMENT0 0xff -#define V_ELEMENT0(x) ((x) << S_ELEMENT0) -#define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0) - -#define S_ELEMENT1 8 -#define M_ELEMENT1 0xff -#define V_ELEMENT1(x) ((x) << S_ELEMENT1) -#define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1) - -#define S_ELEMENT2 16 -#define M_ELEMENT2 0xff -#define V_ELEMENT2(x) ((x) << S_ELEMENT2) -#define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2) - -#define S_ELEMENT3 24 -#define M_ELEMENT3 0xff -#define V_ELEMENT3(x) ((x) << S_ELEMENT3) -#define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3) - -#define A_TP_BACKOFF1 0x354 -#define A_TP_BACKOFF2 0x358 -#define A_TP_BACKOFF3 0x35c -#define A_TP_PARA_REG0 0x360 - -#define S_VAR_MULT 0 -#define M_VAR_MULT 0xf -#define V_VAR_MULT(x) ((x) << S_VAR_MULT) -#define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT) - -#define S_VAR_GAIN 4 -#define M_VAR_GAIN 0xf -#define V_VAR_GAIN(x) ((x) << S_VAR_GAIN) -#define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN) - -#define S_SRTT_GAIN 8 -#define M_SRTT_GAIN 0xf -#define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN) -#define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN) - -#define S_RTTVAR_INIT 12 -#define M_RTTVAR_INIT 0xf -#define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT) -#define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT) - -#define S_DUP_THRESH 20 -#define M_DUP_THRESH 0xf -#define V_DUP_THRESH(x) ((x) << S_DUP_THRESH) -#define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH) - -#define S_INIT_CONG_WIN 24 -#define M_INIT_CONG_WIN 0x7 -#define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN) -#define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN) - -#define A_TP_PARA_REG1 0x364 - -#define S_INITIAL_SLOW_START_THRESHOLD 0 -#define M_INITIAL_SLOW_START_THRESHOLD 0xffff -#define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD) -#define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD) - -#define S_RECEIVE_BUFFER_SIZE 16 -#define M_RECEIVE_BUFFER_SIZE 0xffff -#define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE) -#define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE) - -#define A_TP_PARA_REG2 0x368 - -#define S_RX_COALESCE_SIZE 0 -#define M_RX_COALESCE_SIZE 0xffff -#define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE) -#define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE) - -#define S_MAX_RX_SIZE 16 -#define M_MAX_RX_SIZE 0xffff -#define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE) -#define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE) - -#define A_TP_PARA_REG3 0x36c - -#define S_RX_COALESCING_PSH_DELIVER 0 -#define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER) -#define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U) - -#define S_RX_COALESCING_ENABLE 1 -#define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE) -#define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U) - -#define S_TAHOE_ENABLE 2 -#define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE) -#define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U) - -#define S_MAX_REORDER_FRAGMENTS 12 -#define M_MAX_REORDER_FRAGMENTS 0x7 -#define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS) -#define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS) - -#define A_TP_TIMER_RESOLUTION 0x390 - -#define S_DELAYED_ACK_TIMER_RESOLUTION 0 -#define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f -#define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION) -#define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION) - -#define S_GENERIC_TIMER_RESOLUTION 16 -#define M_GENERIC_TIMER_RESOLUTION 0x3f -#define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION) -#define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION) - -#define A_TP_2MSL 0x394 - -#define S_2MSL 0 -#define M_2MSL 0x3fffffff -#define V_2MSL(x) ((x) << S_2MSL) -#define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL) - -#define A_TP_RXT_MIN 0x398 - -#define S_RETRANSMIT_TIMER_MIN 0 -#define M_RETRANSMIT_TIMER_MIN 0xffff -#define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN) -#define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN) - -#define A_TP_RXT_MAX 0x39c - -#define S_RETRANSMIT_TIMER_MAX 0 -#define M_RETRANSMIT_TIMER_MAX 0x3fffffff -#define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX) -#define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX) - -#define A_TP_PERS_MIN 0x3a0 - -#define S_PERSIST_TIMER_MIN 0 -#define M_PERSIST_TIMER_MIN 0xffff -#define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN) -#define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN) - -#define A_TP_PERS_MAX 0x3a4 - -#define S_PERSIST_TIMER_MAX 0 -#define M_PERSIST_TIMER_MAX 0x3fffffff -#define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX) -#define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX) - -#define A_TP_KEEP_IDLE 0x3ac - -#define S_KEEP_ALIVE_IDLE_TIME 0 -#define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff -#define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME) -#define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME) - -#define A_TP_KEEP_INTVL 0x3b0 - -#define S_KEEP_ALIVE_INTERVAL_TIME 0 -#define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff -#define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME) -#define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME) - -#define A_TP_INIT_SRTT 0x3b4 - -#define S_INITIAL_SRTT 0 -#define M_INITIAL_SRTT 0xffff -#define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT) -#define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT) - -#define A_TP_DACK_TIME 0x3b8 - -#define S_DELAYED_ACK_TIME 0 -#define M_DELAYED_ACK_TIME 0x7ff -#define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME) -#define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME) - -#define A_TP_FINWAIT2_TIME 0x3bc - -#define S_FINWAIT2_TIME 0 -#define M_FINWAIT2_TIME 0x3fffffff -#define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME) -#define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME) - -#define A_TP_FAST_FINWAIT2_TIME 0x3c0 - -#define S_FAST_FINWAIT2_TIME 0 -#define M_FAST_FINWAIT2_TIME 0x3fffffff -#define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME) -#define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME) - -#define A_TP_SHIFT_CNT 0x3c4 - -#define S_KEEPALIVE_MAX 0 -#define M_KEEPALIVE_MAX 0xff -#define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX) -#define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX) - -#define S_WINDOWPROBE_MAX 8 -#define M_WINDOWPROBE_MAX 0xff -#define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX) -#define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX) - -#define S_RETRANSMISSION_MAX 16 -#define M_RETRANSMISSION_MAX 0xff -#define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX) -#define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX) - -#define S_SYN_MAX 24 -#define M_SYN_MAX 0xff -#define V_SYN_MAX(x) ((x) << S_SYN_MAX) -#define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX) - -#define A_TP_QOS_REG0 0x3e0 - -#define S_L3_VALUE 0 -#define M_L3_VALUE 0x3f -#define V_L3_VALUE(x) ((x) << S_L3_VALUE) -#define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE) - -#define A_TP_QOS_REG1 0x3e4 -#define A_TP_QOS_REG2 0x3e8 -#define A_TP_QOS_REG3 0x3ec -#define A_TP_QOS_REG4 0x3f0 -#define A_TP_QOS_REG5 0x3f4 -#define A_TP_QOS_REG6 0x3f8 -#define A_TP_QOS_REG7 0x3fc -#define A_TP_MTU_REG0 0x404 -#define A_TP_MTU_REG1 0x408 -#define A_TP_MTU_REG2 0x40c -#define A_TP_MTU_REG3 0x410 -#define A_TP_MTU_REG4 0x414 -#define A_TP_MTU_REG5 0x418 -#define A_TP_MTU_REG6 0x41c -#define A_TP_MTU_REG7 0x420 -#define A_TP_RESET 0x44c - -#define S_TP_RESET 0 -#define V_TP_RESET(x) ((x) << S_TP_RESET) -#define F_TP_RESET V_TP_RESET(1U) - -#define S_CM_MEMMGR_INIT 1 -#define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT) -#define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U) - -#define A_TP_MIB_INDEX 0x450 -#define A_TP_MIB_DATA 0x454 -#define A_TP_SYNC_TIME_HI 0x458 -#define A_TP_SYNC_TIME_LO 0x45c -#define A_TP_CM_MM_RX_FLST_BASE 0x460 - -#define S_CM_MEMMGR_RX_FREE_LIST_BASE 0 -#define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff -#define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE) -#define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE) - -#define A_TP_CM_MM_TX_FLST_BASE 0x464 - -#define S_CM_MEMMGR_TX_FREE_LIST_BASE 0 -#define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff -#define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE) -#define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE) - -#define A_TP_CM_MM_P_FLST_BASE 0x468 - -#define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0 -#define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff -#define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) -#define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) - -#define A_TP_CM_MM_MAX_P 0x46c - -#define S_CM_MEMMGR_MAX_PSTRUCT 0 -#define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff -#define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT) -#define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT) - -#define A_TP_INT_ENABLE 0x470 - -#define S_TX_FREE_LIST_EMPTY 0 -#define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY) -#define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U) - -#define S_RX_FREE_LIST_EMPTY 1 -#define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY) -#define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U) - -#define A_TP_INT_CAUSE 0x474 -#define A_TP_TIMER_SEPARATOR 0x4a4 - -#define S_DISABLE_PAST_TIMER_INSERTION 0 -#define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION) -#define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U) - -#define S_MODULATION_TIMER_SEPARATOR 1 -#define M_MODULATION_TIMER_SEPARATOR 0x7fff -#define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR) -#define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR) - -#define S_GLOBAL_TIMER_SEPARATOR 16 -#define M_GLOBAL_TIMER_SEPARATOR 0xffff -#define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR) -#define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR) - -#define A_TP_CM_FC_MODE 0x4b0 -#define A_TP_PC_CONGESTION_CNTL 0x4b4 -#define A_TP_TX_DROP_CONFIG 0x4b8 - -#define S_ENABLE_TX_DROP 31 -#define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP) -#define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U) - -#define S_ENABLE_TX_ERROR 30 -#define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR) -#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U) - -#define S_DROP_TICKS_CNT 4 -#define M_DROP_TICKS_CNT 0x3ffffff -#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT) -#define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT) - -#define S_NUM_PKTS_DROPPED 0 -#define M_NUM_PKTS_DROPPED 0xf -#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED) -#define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED) - -#define A_TP_TX_DROP_COUNT 0x4bc - -/* RAT registers */ -#define A_RAT_ROUTE_CONTROL 0x580 - -#define S_USE_ROUTE_TABLE 0 -#define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE) -#define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U) - -#define S_ENABLE_CSPI 1 -#define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI) -#define F_ENABLE_CSPI V_ENABLE_CSPI(1U) - -#define S_ENABLE_PCIX 2 -#define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX) -#define F_ENABLE_PCIX V_ENABLE_PCIX(1U) - -#define A_RAT_ROUTE_TABLE_INDEX 0x584 - -#define S_ROUTE_TABLE_INDEX 0 -#define M_ROUTE_TABLE_INDEX 0xf -#define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX) -#define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX) - -#define A_RAT_ROUTE_TABLE_DATA 0x588 -#define A_RAT_NO_ROUTE 0x58c - -#define S_CPL_OPCODE 0 -#define M_CPL_OPCODE 0xff -#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) -#define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE) - -#define A_RAT_INTR_ENABLE 0x590 - -#define S_ZEROROUTEERROR 0 -#define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR) -#define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U) - -#define S_CSPIFRAMINGERROR 1 -#define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR) -#define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U) - -#define S_SGEFRAMINGERROR 2 -#define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR) -#define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U) - -#define S_TPFRAMINGERROR 3 -#define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR) -#define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U) - -#define A_RAT_INTR_CAUSE 0x594 - -/* CSPI registers */ -#define A_CSPI_RX_AE_WM 0x810 -#define A_CSPI_RX_AF_WM 0x814 -#define A_CSPI_CALENDAR_LEN 0x818 - -#define S_CALENDARLENGTH 0 -#define M_CALENDARLENGTH 0xffff -#define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH) -#define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH) - -#define A_CSPI_FIFO_STATUS_ENABLE 0x820 - -#define S_FIFOSTATUSENABLE 0 -#define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE) -#define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U) - -#define A_CSPI_MAXBURST1_MAXBURST2 0x828 - -#define S_MAXBURST1 0 -#define M_MAXBURST1 0xffff -#define V_MAXBURST1(x) ((x) << S_MAXBURST1) -#define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1) - -#define S_MAXBURST2 16 -#define M_MAXBURST2 0xffff -#define V_MAXBURST2(x) ((x) << S_MAXBURST2) -#define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2) - -#define A_CSPI_TRAIN 0x82c - -#define S_CSPI_TRAIN_ALPHA 0 -#define M_CSPI_TRAIN_ALPHA 0xffff -#define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA) -#define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA) - -#define S_CSPI_TRAIN_DATA_MAXT 16 -#define M_CSPI_TRAIN_DATA_MAXT 0xffff -#define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT) -#define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT) - -#define A_CSPI_INTR_STATUS 0x848 - -#define S_DIP4ERR 0 -#define V_DIP4ERR(x) ((x) << S_DIP4ERR) -#define F_DIP4ERR V_DIP4ERR(1U) - -#define S_RXDROP 1 -#define V_RXDROP(x) ((x) << S_RXDROP) -#define F_RXDROP V_RXDROP(1U) - -#define S_TXDROP 2 -#define V_TXDROP(x) ((x) << S_TXDROP) -#define F_TXDROP V_TXDROP(1U) - -#define S_RXOVERFLOW 3 -#define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW) -#define F_RXOVERFLOW V_RXOVERFLOW(1U) - -#define S_RAMPARITYERR 4 -#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR) -#define F_RAMPARITYERR V_RAMPARITYERR(1U) - -#define A_CSPI_INTR_ENABLE 0x84c - -/* ESPI registers */ -#define A_ESPI_SCH_TOKEN0 0x880 - -#define S_SCHTOKEN0 0 -#define M_SCHTOKEN0 0xffff -#define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0) -#define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0) - -#define A_ESPI_SCH_TOKEN1 0x884 - -#define S_SCHTOKEN1 0 -#define M_SCHTOKEN1 0xffff -#define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1) -#define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1) - -#define A_ESPI_SCH_TOKEN2 0x888 - -#define S_SCHTOKEN2 0 -#define M_SCHTOKEN2 0xffff -#define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2) -#define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2) - -#define A_ESPI_SCH_TOKEN3 0x88c - -#define S_SCHTOKEN3 0 -#define M_SCHTOKEN3 0xffff -#define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3) -#define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3) - -#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890 - -#define S_ALMOSTEMPTY 0 -#define M_ALMOSTEMPTY 0xffff -#define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY) -#define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY) - -#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894 - -#define S_ALMOSTFULL 0 -#define M_ALMOSTFULL 0xffff -#define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL) -#define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL) - -#define A_ESPI_CALENDAR_LENGTH 0x898 -#define A_PORT_CONFIG 0x89c - -#define S_RX_NPORTS 0 -#define M_RX_NPORTS 0xff -#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS) -#define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS) - -#define S_TX_NPORTS 8 -#define M_TX_NPORTS 0xff -#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS) -#define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS) - -#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0 - -#define S_RXSTATUSENABLE 0 -#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE) -#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U) - -#define S_TXDROPENABLE 1 -#define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE) -#define F_TXDROPENABLE V_TXDROPENABLE(1U) - -#define S_RXENDIANMODE 2 -#define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE) -#define F_RXENDIANMODE V_RXENDIANMODE(1U) - -#define S_TXENDIANMODE 3 -#define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE) -#define F_TXENDIANMODE V_TXENDIANMODE(1U) - -#define S_INTEL1010MODE 4 -#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE) -#define F_INTEL1010MODE V_INTEL1010MODE(1U) - -#define A_ESPI_MAXBURST1_MAXBURST2 0x8a8 -#define A_ESPI_TRAIN 0x8ac - -#define S_MAXTRAINALPHA 0 -#define M_MAXTRAINALPHA 0xffff -#define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA) -#define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA) - -#define S_MAXTRAINDATA 16 -#define M_MAXTRAINDATA 0xffff -#define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA) -#define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA) - -#define A_RAM_STATUS 0x8b0 - -#define S_RXFIFOPARITYERROR 0 -#define M_RXFIFOPARITYERROR 0x3ff -#define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR) -#define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR) - -#define S_TXFIFOPARITYERROR 10 -#define M_TXFIFOPARITYERROR 0x3ff -#define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR) -#define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR) - -#define S_RXFIFOOVERFLOW 20 -#define M_RXFIFOOVERFLOW 0x3ff -#define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW) -#define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW) - -#define A_TX_DROP_COUNT0 0x8b4 - -#define S_TXPORT0DROPCNT 0 -#define M_TXPORT0DROPCNT 0xffff -#define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT) -#define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT) - -#define S_TXPORT1DROPCNT 16 -#define M_TXPORT1DROPCNT 0xffff -#define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT) -#define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT) - -#define A_TX_DROP_COUNT1 0x8b8 - -#define S_TXPORT2DROPCNT 0 -#define M_TXPORT2DROPCNT 0xffff -#define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT) -#define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT) - -#define S_TXPORT3DROPCNT 16 -#define M_TXPORT3DROPCNT 0xffff -#define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT) -#define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT) - -#define A_RX_DROP_COUNT0 0x8bc - -#define S_RXPORT0DROPCNT 0 -#define M_RXPORT0DROPCNT 0xffff -#define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT) -#define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT) - -#define S_RXPORT1DROPCNT 16 -#define M_RXPORT1DROPCNT 0xffff -#define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT) -#define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT) - -#define A_RX_DROP_COUNT1 0x8c0 - -#define S_RXPORT2DROPCNT 0 -#define M_RXPORT2DROPCNT 0xffff -#define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT) -#define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT) - -#define S_RXPORT3DROPCNT 16 -#define M_RXPORT3DROPCNT 0xffff -#define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT) -#define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT) - -#define A_DIP4_ERROR_COUNT 0x8c4 - -#define S_DIP4ERRORCNT 0 -#define M_DIP4ERRORCNT 0xfff -#define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT) -#define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT) - -#define S_DIP4ERRORCNTSHADOW 12 -#define M_DIP4ERRORCNTSHADOW 0xfff -#define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW) -#define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW) - -#define S_TRICN_RX_TRAIN_ERR 24 -#define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR) -#define F_TRICN_RX_TRAIN_ERR V_TRICN_RX_TRAIN_ERR(1U) - -#define S_TRICN_RX_TRAINING 25 -#define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING) -#define F_TRICN_RX_TRAINING V_TRICN_RX_TRAINING(1U) - -#define S_TRICN_RX_TRAIN_OK 26 -#define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK) -#define F_TRICN_RX_TRAIN_OK V_TRICN_RX_TRAIN_OK(1U) - -#define A_ESPI_INTR_STATUS 0x8c8 - -#define S_DIP2PARITYERR 5 -#define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR) -#define F_DIP2PARITYERR V_DIP2PARITYERR(1U) - -#define A_ESPI_INTR_ENABLE 0x8cc -#define A_RX_DROP_THRESHOLD 0x8d0 -#define A_ESPI_RX_RESET 0x8ec - -#define S_ESPI_RX_LNK_RST 0 -#define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST) -#define F_ESPI_RX_LNK_RST V_ESPI_RX_LNK_RST(1U) - -#define S_ESPI_RX_CORE_RST 1 -#define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST) -#define F_ESPI_RX_CORE_RST V_ESPI_RX_CORE_RST(1U) - -#define S_RX_CLK_STATUS 2 -#define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS) -#define F_RX_CLK_STATUS V_RX_CLK_STATUS(1U) - -#define A_ESPI_MISC_CONTROL 0x8f0 - -#define S_OUT_OF_SYNC_COUNT 0 -#define M_OUT_OF_SYNC_COUNT 0xf -#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT) -#define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT) - -#define S_DIP2_COUNT_MODE_ENABLE 4 -#define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE) -#define F_DIP2_COUNT_MODE_ENABLE V_DIP2_COUNT_MODE_ENABLE(1U) - -#define S_DIP2_PARITY_ERR_THRES 5 -#define M_DIP2_PARITY_ERR_THRES 0xf -#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES) -#define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES) - -#define S_DIP4_THRES 9 -#define M_DIP4_THRES 0xfff -#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES) -#define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES) - -#define S_DIP4_THRES_ENABLE 21 -#define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE) -#define F_DIP4_THRES_ENABLE V_DIP4_THRES_ENABLE(1U) - -#define S_FORCE_DISABLE_STATUS 22 -#define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS) -#define F_FORCE_DISABLE_STATUS V_FORCE_DISABLE_STATUS(1U) - -#define S_DYNAMIC_DESKEW 23 -#define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW) -#define F_DYNAMIC_DESKEW V_DYNAMIC_DESKEW(1U) - -#define S_MONITORED_PORT_NUM 25 -#define M_MONITORED_PORT_NUM 0x3 -#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM) -#define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM) - -#define S_MONITORED_DIRECTION 27 -#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION) -#define F_MONITORED_DIRECTION V_MONITORED_DIRECTION(1U) - -#define S_MONITORED_INTERFACE 28 -#define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE) -#define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U) - -#define A_ESPI_DIP2_ERR_COUNT 0x8f4 - -#define S_DIP2_ERR_CNT 0 -#define M_DIP2_ERR_CNT 0xf -#define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT) -#define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT) - -#define A_ESPI_CMD_ADDR 0x8f8 - -#define S_WRITE_DATA 0 -#define M_WRITE_DATA 0xff -#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA) -#define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA) - -#define S_REGISTER_OFFSET 8 -#define M_REGISTER_OFFSET 0xf -#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET) -#define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET) - -#define S_CHANNEL_ADDR 12 -#define M_CHANNEL_ADDR 0xf -#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR) -#define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR) - -#define S_MODULE_ADDR 16 -#define M_MODULE_ADDR 0x3 -#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR) -#define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR) - -#define S_BUNDLE_ADDR 20 -#define M_BUNDLE_ADDR 0x3 -#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR) -#define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR) - -#define S_SPI4_COMMAND 24 -#define M_SPI4_COMMAND 0xff -#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND) -#define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND) - -#define A_ESPI_GOSTAT 0x8fc - -#define S_READ_DATA 0 -#define M_READ_DATA 0xff -#define V_READ_DATA(x) ((x) << S_READ_DATA) -#define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA) - -#define S_ESPI_CMD_BUSY 8 -#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY) -#define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U) - -#define S_ERROR_ACK 9 -#define V_ERROR_ACK(x) ((x) << S_ERROR_ACK) -#define F_ERROR_ACK V_ERROR_ACK(1U) - -#define S_UNMAPPED_ERR 10 -#define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR) -#define F_UNMAPPED_ERR V_UNMAPPED_ERR(1U) - -#define S_TRANSACTION_TIMER 16 -#define M_TRANSACTION_TIMER 0xff -#define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER) -#define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER) - - -/* ULP registers */ -#define A_ULP_ULIMIT 0x980 -#define A_ULP_TAGMASK 0x984 -#define A_ULP_HREG_INDEX 0x988 -#define A_ULP_HREG_DATA 0x98c -#define A_ULP_INT_ENABLE 0x990 -#define A_ULP_INT_CAUSE 0x994 - -#define S_HREG_PAR_ERR 0 -#define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR) -#define F_HREG_PAR_ERR V_HREG_PAR_ERR(1U) - -#define S_EGRS_DATA_PAR_ERR 1 -#define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR) -#define F_EGRS_DATA_PAR_ERR V_EGRS_DATA_PAR_ERR(1U) - -#define S_INGRS_DATA_PAR_ERR 2 -#define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR) -#define F_INGRS_DATA_PAR_ERR V_INGRS_DATA_PAR_ERR(1U) - -#define S_PM_INTR 3 -#define V_PM_INTR(x) ((x) << S_PM_INTR) -#define F_PM_INTR V_PM_INTR(1U) - -#define S_PM_E2C_SYNC_ERR 4 -#define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR) -#define F_PM_E2C_SYNC_ERR V_PM_E2C_SYNC_ERR(1U) - -#define S_PM_C2E_SYNC_ERR 5 -#define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR) -#define F_PM_C2E_SYNC_ERR V_PM_C2E_SYNC_ERR(1U) - -#define S_PM_E2C_EMPTY_ERR 6 -#define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR) -#define F_PM_E2C_EMPTY_ERR V_PM_E2C_EMPTY_ERR(1U) - -#define S_PM_C2E_EMPTY_ERR 7 -#define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR) -#define F_PM_C2E_EMPTY_ERR V_PM_C2E_EMPTY_ERR(1U) - -#define S_PM_PAR_ERR 8 -#define M_PM_PAR_ERR 0xffff -#define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR) -#define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR) - -#define S_PM_E2C_WRT_FULL 24 -#define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL) -#define F_PM_E2C_WRT_FULL V_PM_E2C_WRT_FULL(1U) - -#define S_PM_C2E_WRT_FULL 25 -#define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL) -#define F_PM_C2E_WRT_FULL V_PM_C2E_WRT_FULL(1U) - -#define A_ULP_PIO_CTRL 0x998 - -/* PL registers */ -#define A_PL_ENABLE 0xa00 - -#define S_PL_INTR_SGE_ERR 0 -#define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR) -#define F_PL_INTR_SGE_ERR V_PL_INTR_SGE_ERR(1U) - -#define S_PL_INTR_SGE_DATA 1 -#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA) -#define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U) - -#define S_PL_INTR_MC3 2 -#define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3) -#define F_PL_INTR_MC3 V_PL_INTR_MC3(1U) - -#define S_PL_INTR_MC4 3 -#define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4) -#define F_PL_INTR_MC4 V_PL_INTR_MC4(1U) - -#define S_PL_INTR_MC5 4 -#define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5) -#define F_PL_INTR_MC5 V_PL_INTR_MC5(1U) - -#define S_PL_INTR_RAT 5 -#define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT) -#define F_PL_INTR_RAT V_PL_INTR_RAT(1U) - -#define S_PL_INTR_TP 6 -#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP) -#define F_PL_INTR_TP V_PL_INTR_TP(1U) - -#define S_PL_INTR_ULP 7 -#define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP) -#define F_PL_INTR_ULP V_PL_INTR_ULP(1U) - -#define S_PL_INTR_ESPI 8 -#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI) -#define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U) - -#define S_PL_INTR_CSPI 9 -#define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI) -#define F_PL_INTR_CSPI V_PL_INTR_CSPI(1U) - -#define S_PL_INTR_PCIX 10 -#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX) -#define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U) - -#define S_PL_INTR_EXT 11 -#define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT) -#define F_PL_INTR_EXT V_PL_INTR_EXT(1U) - -#define A_PL_CAUSE 0xa04 - -/* MC5 registers */ -#define A_MC5_CONFIG 0xc04 - -#define S_MODE 0 -#define V_MODE(x) ((x) << S_MODE) -#define F_MODE V_MODE(1U) - -#define S_TCAM_RESET 1 -#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET) -#define F_TCAM_RESET V_TCAM_RESET(1U) - -#define S_TCAM_READY 2 -#define V_TCAM_READY(x) ((x) << S_TCAM_READY) -#define F_TCAM_READY V_TCAM_READY(1U) - -#define S_DBGI_ENABLE 4 -#define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE) -#define F_DBGI_ENABLE V_DBGI_ENABLE(1U) - -#define S_M_BUS_ENABLE 5 -#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE) -#define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U) - -#define S_PARITY_ENABLE 6 -#define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE) -#define F_PARITY_ENABLE V_PARITY_ENABLE(1U) - -#define S_SYN_ISSUE_MODE 7 -#define M_SYN_ISSUE_MODE 0x3 -#define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE) -#define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE) - -#define S_BUILD 16 -#define V_BUILD(x) ((x) << S_BUILD) -#define F_BUILD V_BUILD(1U) - -#define S_COMPRESSION_ENABLE 17 -#define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE) -#define F_COMPRESSION_ENABLE V_COMPRESSION_ENABLE(1U) - -#define S_NUM_LIP 18 -#define M_NUM_LIP 0x3f -#define V_NUM_LIP(x) ((x) << S_NUM_LIP) -#define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP) - -#define S_TCAM_PART_CNT 24 -#define M_TCAM_PART_CNT 0x3 -#define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT) -#define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT) - -#define S_TCAM_PART_TYPE 26 -#define M_TCAM_PART_TYPE 0x3 -#define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE) -#define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE) - -#define S_TCAM_PART_SIZE 28 -#define M_TCAM_PART_SIZE 0x3 -#define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE) -#define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE) - -#define S_TCAM_PART_TYPE_HI 30 -#define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI) -#define F_TCAM_PART_TYPE_HI V_TCAM_PART_TYPE_HI(1U) - -#define A_MC5_SIZE 0xc08 - -#define S_SIZE 0 -#define M_SIZE 0x3fffff -#define V_SIZE(x) ((x) << S_SIZE) -#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE) - -#define A_MC5_ROUTING_TABLE_INDEX 0xc0c - -#define S_START_OF_ROUTING_TABLE 0 -#define M_START_OF_ROUTING_TABLE 0x3fffff -#define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE) -#define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE) - -#define A_MC5_SERVER_INDEX 0xc14 - -#define S_START_OF_SERVER_INDEX 0 -#define M_START_OF_SERVER_INDEX 0x3fffff -#define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX) -#define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX) - -#define A_MC5_LIP_RAM_ADDR 0xc18 - -#define S_LOCAL_IP_RAM_ADDR 0 -#define M_LOCAL_IP_RAM_ADDR 0x3f -#define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR) -#define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR) - -#define S_RAM_WRITE_ENABLE 8 -#define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE) -#define F_RAM_WRITE_ENABLE V_RAM_WRITE_ENABLE(1U) - -#define A_MC5_LIP_RAM_DATA 0xc1c -#define A_MC5_RSP_LATENCY 0xc20 - -#define S_SEARCH_RESPONSE_LATENCY 0 -#define M_SEARCH_RESPONSE_LATENCY 0x1f -#define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY) -#define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY) - -#define S_LEARN_RESPONSE_LATENCY 8 -#define M_LEARN_RESPONSE_LATENCY 0x1f -#define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY) -#define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY) - -#define A_MC5_PARITY_LATENCY 0xc24 - -#define S_SRCHLAT 0 -#define M_SRCHLAT 0x1f -#define V_SRCHLAT(x) ((x) << S_SRCHLAT) -#define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT) - -#define S_PARLAT 8 -#define M_PARLAT 0x1f -#define V_PARLAT(x) ((x) << S_PARLAT) -#define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT) - -#define A_MC5_WR_LRN_VERIFY 0xc28 - -#define S_POVEREN 0 -#define V_POVEREN(x) ((x) << S_POVEREN) -#define F_POVEREN V_POVEREN(1U) - -#define S_LRNVEREN 1 -#define V_LRNVEREN(x) ((x) << S_LRNVEREN) -#define F_LRNVEREN V_LRNVEREN(1U) - -#define S_VWVEREN 2 -#define V_VWVEREN(x) ((x) << S_VWVEREN) -#define F_VWVEREN V_VWVEREN(1U) - -#define A_MC5_PART_ID_INDEX 0xc2c - -#define S_IDINDEX 0 -#define M_IDINDEX 0xf -#define V_IDINDEX(x) ((x) << S_IDINDEX) -#define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX) - -#define A_MC5_RESET_MAX 0xc30 - -#define S_RSTMAX 0 -#define M_RSTMAX 0x1ff -#define V_RSTMAX(x) ((x) << S_RSTMAX) -#define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX) - -#define A_MC5_INT_ENABLE 0xc40 - -#define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 0 -#define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR) -#define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U) - -#define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR 1 -#define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR) -#define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U) - -#define S_MC5_INT_HIT_IN_RT_REGION_ERR 2 -#define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR) -#define F_MC5_INT_HIT_IN_RT_REGION_ERR V_MC5_INT_HIT_IN_RT_REGION_ERR(1U) - -#define S_MC5_INT_MISS_ERR 3 -#define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR) -#define F_MC5_INT_MISS_ERR V_MC5_INT_MISS_ERR(1U) - -#define S_MC5_INT_LIP0_ERR 4 -#define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR) -#define F_MC5_INT_LIP0_ERR V_MC5_INT_LIP0_ERR(1U) - -#define S_MC5_INT_LIP_MISS_ERR 5 -#define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR) -#define F_MC5_INT_LIP_MISS_ERR V_MC5_INT_LIP_MISS_ERR(1U) - -#define S_MC5_INT_PARITY_ERR 6 -#define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR) -#define F_MC5_INT_PARITY_ERR V_MC5_INT_PARITY_ERR(1U) - -#define S_MC5_INT_ACTIVE_REGION_FULL 7 -#define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL) -#define F_MC5_INT_ACTIVE_REGION_FULL V_MC5_INT_ACTIVE_REGION_FULL(1U) - -#define S_MC5_INT_NFA_SRCH_ERR 8 -#define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR) -#define F_MC5_INT_NFA_SRCH_ERR V_MC5_INT_NFA_SRCH_ERR(1U) - -#define S_MC5_INT_SYN_COOKIE 9 -#define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE) -#define F_MC5_INT_SYN_COOKIE V_MC5_INT_SYN_COOKIE(1U) - -#define S_MC5_INT_SYN_COOKIE_BAD 10 -#define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD) -#define F_MC5_INT_SYN_COOKIE_BAD V_MC5_INT_SYN_COOKIE_BAD(1U) - -#define S_MC5_INT_SYN_COOKIE_OFF 11 -#define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF) -#define F_MC5_INT_SYN_COOKIE_OFF V_MC5_INT_SYN_COOKIE_OFF(1U) - -#define S_MC5_INT_UNKNOWN_CMD 15 -#define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD) -#define F_MC5_INT_UNKNOWN_CMD V_MC5_INT_UNKNOWN_CMD(1U) - -#define S_MC5_INT_REQUESTQ_PARITY_ERR 16 -#define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR) -#define F_MC5_INT_REQUESTQ_PARITY_ERR V_MC5_INT_REQUESTQ_PARITY_ERR(1U) - -#define S_MC5_INT_DISPATCHQ_PARITY_ERR 17 -#define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR) -#define F_MC5_INT_DISPATCHQ_PARITY_ERR V_MC5_INT_DISPATCHQ_PARITY_ERR(1U) - -#define S_MC5_INT_DEL_ACT_EMPTY 18 -#define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY) -#define F_MC5_INT_DEL_ACT_EMPTY V_MC5_INT_DEL_ACT_EMPTY(1U) - -#define A_MC5_INT_CAUSE 0xc44 -#define A_MC5_INT_TID 0xc48 -#define A_MC5_INT_PTID 0xc4c -#define A_MC5_DBGI_CONFIG 0xc74 -#define A_MC5_DBGI_REQ_CMD 0xc78 - -#define S_CMDMODE 0 -#define M_CMDMODE 0x7 -#define V_CMDMODE(x) ((x) << S_CMDMODE) -#define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE) - -#define S_SADRSEL 4 -#define V_SADRSEL(x) ((x) << S_SADRSEL) -#define F_SADRSEL V_SADRSEL(1U) - -#define S_WRITE_BURST_SIZE 22 -#define M_WRITE_BURST_SIZE 0x3ff -#define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE) -#define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE) - -#define A_MC5_DBGI_REQ_ADDR0 0xc7c -#define A_MC5_DBGI_REQ_ADDR1 0xc80 -#define A_MC5_DBGI_REQ_ADDR2 0xc84 -#define A_MC5_DBGI_REQ_DATA0 0xc88 -#define A_MC5_DBGI_REQ_DATA1 0xc8c -#define A_MC5_DBGI_REQ_DATA2 0xc90 -#define A_MC5_DBGI_REQ_DATA3 0xc94 -#define A_MC5_DBGI_REQ_DATA4 0xc98 -#define A_MC5_DBGI_REQ_MASK0 0xc9c -#define A_MC5_DBGI_REQ_MASK1 0xca0 -#define A_MC5_DBGI_REQ_MASK2 0xca4 -#define A_MC5_DBGI_REQ_MASK3 0xca8 -#define A_MC5_DBGI_REQ_MASK4 0xcac -#define A_MC5_DBGI_RSP_STATUS 0xcb0 - -#define S_DBGI_RSP_VALID 0 -#define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID) -#define F_DBGI_RSP_VALID V_DBGI_RSP_VALID(1U) - -#define S_DBGI_RSP_HIT 1 -#define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT) -#define F_DBGI_RSP_HIT V_DBGI_RSP_HIT(1U) - -#define S_DBGI_RSP_ERR 2 -#define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR) -#define F_DBGI_RSP_ERR V_DBGI_RSP_ERR(1U) - -#define S_DBGI_RSP_ERR_REASON 8 -#define M_DBGI_RSP_ERR_REASON 0x7 -#define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON) -#define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON) - -#define A_MC5_DBGI_RSP_DATA0 0xcb4 -#define A_MC5_DBGI_RSP_DATA1 0xcb8 -#define A_MC5_DBGI_RSP_DATA2 0xcbc -#define A_MC5_DBGI_RSP_DATA3 0xcc0 -#define A_MC5_DBGI_RSP_DATA4 0xcc4 -#define A_MC5_DBGI_RSP_LAST_CMD 0xcc8 -#define A_MC5_POPEN_DATA_WR_CMD 0xccc -#define A_MC5_POPEN_MASK_WR_CMD 0xcd0 -#define A_MC5_AOPEN_SRCH_CMD 0xcd4 -#define A_MC5_AOPEN_LRN_CMD 0xcd8 -#define A_MC5_SYN_SRCH_CMD 0xcdc -#define A_MC5_SYN_LRN_CMD 0xce0 -#define A_MC5_ACK_SRCH_CMD 0xce4 -#define A_MC5_ACK_LRN_CMD 0xce8 -#define A_MC5_ILOOKUP_CMD 0xcec -#define A_MC5_ELOOKUP_CMD 0xcf0 -#define A_MC5_DATA_WRITE_CMD 0xcf4 -#define A_MC5_DATA_READ_CMD 0xcf8 -#define A_MC5_MASK_WRITE_CMD 0xcfc - -/* PCICFG registers */ -#define A_PCICFG_PM_CSR 0x44 -#define A_PCICFG_VPD_ADDR 0x4a - -#define S_VPD_ADDR 0 -#define M_VPD_ADDR 0x7fff -#define V_VPD_ADDR(x) ((x) << S_VPD_ADDR) -#define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR) - -#define S_VPD_OP_FLAG 15 -#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG) -#define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U) - -#define A_PCICFG_VPD_DATA 0x4c -#define A_PCICFG_PCIX_CMD 0x60 -#define A_PCICFG_INTR_ENABLE 0xf4 - -#define S_MASTER_PARITY_ERR 0 -#define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR) -#define F_MASTER_PARITY_ERR V_MASTER_PARITY_ERR(1U) - -#define S_SIG_TARGET_ABORT 1 -#define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT) -#define F_SIG_TARGET_ABORT V_SIG_TARGET_ABORT(1U) - -#define S_RCV_TARGET_ABORT 2 -#define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT) -#define F_RCV_TARGET_ABORT V_RCV_TARGET_ABORT(1U) - -#define S_RCV_MASTER_ABORT 3 -#define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT) -#define F_RCV_MASTER_ABORT V_RCV_MASTER_ABORT(1U) - -#define S_SIG_SYS_ERR 4 -#define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR) -#define F_SIG_SYS_ERR V_SIG_SYS_ERR(1U) - -#define S_DET_PARITY_ERR 5 -#define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR) -#define F_DET_PARITY_ERR V_DET_PARITY_ERR(1U) - -#define S_PIO_PARITY_ERR 6 -#define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR) -#define F_PIO_PARITY_ERR V_PIO_PARITY_ERR(1U) - -#define S_WF_PARITY_ERR 7 -#define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR) -#define F_WF_PARITY_ERR V_WF_PARITY_ERR(1U) - -#define S_RF_PARITY_ERR 8 -#define M_RF_PARITY_ERR 0x3 -#define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR) -#define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR) - -#define S_CF_PARITY_ERR 10 -#define M_CF_PARITY_ERR 0x3 -#define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR) -#define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR) - -#define A_PCICFG_INTR_CAUSE 0xf8 -#define A_PCICFG_MODE 0xfc - -#define S_PCI_MODE_64BIT 0 -#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT) -#define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U) - -#define S_PCI_MODE_66MHZ 1 -#define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ) -#define F_PCI_MODE_66MHZ V_PCI_MODE_66MHZ(1U) - -#define S_PCI_MODE_PCIX_INITPAT 2 -#define M_PCI_MODE_PCIX_INITPAT 0x7 -#define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT) -#define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT) - -#define S_PCI_MODE_PCIX 5 -#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX) -#define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U) - -#define S_PCI_MODE_CLK 6 -#define M_PCI_MODE_CLK 0x3 -#define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK) -#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK) - -#endif /* _CXGB_REGS_H_ */ diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c deleted file mode 100644 index e9a03fffef1..00000000000 --- a/drivers/net/chelsio/sge.c +++ /dev/null @@ -1,2140 +0,0 @@ -/***************************************************************************** - * * - * File: sge.c * - * $Revision: 1.26 $ * - * $Date: 2005/06/21 18:29:48 $ * - * Description: * - * DMA engine. * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#include "common.h" - -#include <linux/types.h> -#include <linux/errno.h> -#include <linux/pci.h> -#include <linux/ktime.h> -#include <linux/netdevice.h> -#include <linux/etherdevice.h> -#include <linux/if_vlan.h> -#include <linux/skbuff.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/tcp.h> -#include <linux/ip.h> -#include <linux/in.h> -#include <linux/if_arp.h> -#include <linux/slab.h> -#include <linux/prefetch.h> - -#include "cpl5_cmd.h" -#include "sge.h" -#include "regs.h" -#include "espi.h" - -/* This belongs in if_ether.h */ -#define ETH_P_CPL5 0xf - -#define SGE_CMDQ_N 2 -#define SGE_FREELQ_N 2 -#define SGE_CMDQ0_E_N 1024 -#define SGE_CMDQ1_E_N 128 -#define SGE_FREEL_SIZE 4096 -#define SGE_JUMBO_FREEL_SIZE 512 -#define SGE_FREEL_REFILL_THRESH 16 -#define SGE_RESPQ_E_N 1024 -#define SGE_INTRTIMER_NRES 1000 -#define SGE_RX_SM_BUF_SIZE 1536 -#define SGE_TX_DESC_MAX_PLEN 16384 - -#define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4) - -/* - * Period of the TX buffer reclaim timer. This timer does not need to run - * frequently as TX buffers are usually reclaimed by new TX packets. - */ -#define TX_RECLAIM_PERIOD (HZ / 4) - -#define M_CMD_LEN 0x7fffffff -#define V_CMD_LEN(v) (v) -#define G_CMD_LEN(v) ((v) & M_CMD_LEN) -#define V_CMD_GEN1(v) ((v) << 31) -#define V_CMD_GEN2(v) (v) -#define F_CMD_DATAVALID (1 << 1) -#define F_CMD_SOP (1 << 2) -#define V_CMD_EOP(v) ((v) << 3) - -/* - * Command queue, receive buffer list, and response queue descriptors. - */ -#if defined(__BIG_ENDIAN_BITFIELD) -struct cmdQ_e { - u32 addr_lo; - u32 len_gen; - u32 flags; - u32 addr_hi; -}; - -struct freelQ_e { - u32 addr_lo; - u32 len_gen; - u32 gen2; - u32 addr_hi; -}; - -struct respQ_e { - u32 Qsleeping : 4; - u32 Cmdq1CreditReturn : 5; - u32 Cmdq1DmaComplete : 5; - u32 Cmdq0CreditReturn : 5; - u32 Cmdq0DmaComplete : 5; - u32 FreelistQid : 2; - u32 CreditValid : 1; - u32 DataValid : 1; - u32 Offload : 1; - u32 Eop : 1; - u32 Sop : 1; - u32 GenerationBit : 1; - u32 BufferLength; -}; -#elif defined(__LITTLE_ENDIAN_BITFIELD) -struct cmdQ_e { - u32 len_gen; - u32 addr_lo; - u32 addr_hi; - u32 flags; -}; - -struct freelQ_e { - u32 len_gen; - u32 addr_lo; - u32 addr_hi; - u32 gen2; -}; - -struct respQ_e { - u32 BufferLength; - u32 GenerationBit : 1; - u32 Sop : 1; - u32 Eop : 1; - u32 Offload : 1; - u32 DataValid : 1; - u32 CreditValid : 1; - u32 FreelistQid : 2; - u32 Cmdq0DmaComplete : 5; - u32 Cmdq0CreditReturn : 5; - u32 Cmdq1DmaComplete : 5; - u32 Cmdq1CreditReturn : 5; - u32 Qsleeping : 4; -} ; -#endif - -/* - * SW Context Command and Freelist Queue Descriptors - */ -struct cmdQ_ce { - struct sk_buff *skb; - DEFINE_DMA_UNMAP_ADDR(dma_addr); - DEFINE_DMA_UNMAP_LEN(dma_len); -}; - -struct freelQ_ce { - struct sk_buff *skb; - DEFINE_DMA_UNMAP_ADDR(dma_addr); - DEFINE_DMA_UNMAP_LEN(dma_len); -}; - -/* - * SW command, freelist and response rings - */ -struct cmdQ { - unsigned long status; /* HW DMA fetch status */ - unsigned int in_use; /* # of in-use command descriptors */ - unsigned int size; /* # of descriptors */ - unsigned int processed; /* total # of descs HW has processed */ - unsigned int cleaned; /* total # of descs SW has reclaimed */ - unsigned int stop_thres; /* SW TX queue suspend threshold */ - u16 pidx; /* producer index (SW) */ - u16 cidx; /* consumer index (HW) */ - u8 genbit; /* current generation (=valid) bit */ - u8 sop; /* is next entry start of packet? */ - struct cmdQ_e *entries; /* HW command descriptor Q */ - struct cmdQ_ce *centries; /* SW command context descriptor Q */ - dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ - spinlock_t lock; /* Lock to protect cmdQ enqueuing */ -}; - -struct freelQ { - unsigned int credits; /* # of available RX buffers */ - unsigned int size; /* free list capacity */ - u16 pidx; /* producer index (SW) */ - u16 cidx; /* consumer index (HW) */ - u16 rx_buffer_size; /* Buffer size on this free list */ - u16 dma_offset; /* DMA offset to align IP headers */ - u16 recycleq_idx; /* skb recycle q to use */ - u8 genbit; /* current generation (=valid) bit */ - struct freelQ_e *entries; /* HW freelist descriptor Q */ - struct freelQ_ce *centries; /* SW freelist context descriptor Q */ - dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */ -}; - -struct respQ { - unsigned int credits; /* credits to be returned to SGE */ - unsigned int size; /* # of response Q descriptors */ - u16 cidx; /* consumer index (SW) */ - u8 genbit; /* current generation(=valid) bit */ - struct respQ_e *entries; /* HW response descriptor Q */ - dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */ -}; - -/* Bit flags for cmdQ.status */ -enum { - CMDQ_STAT_RUNNING = 1, /* fetch engine is running */ - CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */ -}; - -/* T204 TX SW scheduler */ - -/* Per T204 TX port */ -struct sched_port { - unsigned int avail; /* available bits - quota */ - unsigned int drain_bits_per_1024ns; /* drain rate */ - unsigned int speed; /* drain rate, mbps */ - unsigned int mtu; /* mtu size */ - struct sk_buff_head skbq; /* pending skbs */ -}; - -/* Per T204 device */ -struct sched { - ktime_t last_updated; /* last time quotas were computed */ - unsigned int max_avail; /* max bits to be sent to any port */ - unsigned int port; /* port index (round robin ports) */ - unsigned int num; /* num skbs in per port queues */ - struct sched_port p[MAX_NPORTS]; - struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */ -}; -static void restart_sched(unsigned long); - - -/* - * Main SGE data structure - * - * Interrupts are handled by a single CPU and it is likely that on a MP system - * the application is migrated to another CPU. In that scenario, we try to - * separate the RX(in irq context) and TX state in order to decrease memory - * contention. - */ -struct sge { - struct adapter *adapter; /* adapter backpointer */ - struct net_device *netdev; /* netdevice backpointer */ - struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */ - struct respQ respQ; /* response Q */ - unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */ - unsigned int rx_pkt_pad; /* RX padding for L2 packets */ - unsigned int jumbo_fl; /* jumbo freelist Q index */ - unsigned int intrtimer_nres; /* no-resource interrupt timer */ - unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */ - struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ - struct timer_list espibug_timer; - unsigned long espibug_timeout; - struct sk_buff *espibug_skb[MAX_NPORTS]; - u32 sge_control; /* shadow value of sge control reg */ - struct sge_intr_counts stats; - struct sge_port_stats __percpu *port_stats[MAX_NPORTS]; - struct sched *tx_sched; - struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; -}; - -static const u8 ch_mac_addr[ETH_ALEN] = { - 0x0, 0x7, 0x43, 0x0, 0x0, 0x0 -}; - -/* - * stop tasklet and free all pending skb's - */ -static void tx_sched_stop(struct sge *sge) -{ - struct sched *s = sge->tx_sched; - int i; - - tasklet_kill(&s->sched_tsk); - - for (i = 0; i < MAX_NPORTS; i++) - __skb_queue_purge(&s->p[s->port].skbq); -} - -/* - * t1_sched_update_parms() is called when the MTU or link speed changes. It - * re-computes scheduler parameters to scope with the change. - */ -unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port, - unsigned int mtu, unsigned int speed) -{ - struct sched *s = sge->tx_sched; - struct sched_port *p = &s->p[port]; - unsigned int max_avail_segs; - - pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed); - if (speed) - p->speed = speed; - if (mtu) - p->mtu = mtu; - - if (speed || mtu) { - unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40); - do_div(drain, (p->mtu + 50) * 1000); - p->drain_bits_per_1024ns = (unsigned int) drain; - - if (p->speed < 1000) - p->drain_bits_per_1024ns = - 90 * p->drain_bits_per_1024ns / 100; - } - - if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) { - p->drain_bits_per_1024ns -= 16; - s->max_avail = max(4096U, p->mtu + 16 + 14 + 4); - max_avail_segs = max(1U, 4096 / (p->mtu - 40)); - } else { - s->max_avail = 16384; - max_avail_segs = max(1U, 9000 / (p->mtu - 40)); - } - - pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u " - "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu, - p->speed, s->max_avail, max_avail_segs, - p->drain_bits_per_1024ns); - - return max_avail_segs * (p->mtu - 40); -} - -#if 0 - -/* - * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of - * data that can be pushed per port. - */ -void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val) -{ - struct sched *s = sge->tx_sched; - unsigned int i; - - s->max_avail = val; - for (i = 0; i < MAX_NPORTS; i++) - t1_sched_update_parms(sge, i, 0, 0); -} - -/* - * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port - * is draining. - */ -void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port, - unsigned int val) -{ - struct sched *s = sge->tx_sched; - struct sched_port *p = &s->p[port]; - p->drain_bits_per_1024ns = val * 1024 / 1000; - t1_sched_update_parms(sge, port, 0, 0); -} - -#endif /* 0 */ - - -/* - * get_clock() implements a ns clock (see ktime_get) - */ -static inline ktime_t get_clock(void) -{ - struct timespec ts; - - ktime_get_ts(&ts); - return timespec_to_ktime(ts); -} - -/* - * tx_sched_init() allocates resources and does basic initialization. - */ -static int tx_sched_init(struct sge *sge) -{ - struct sched *s; - int i; - - s = kzalloc(sizeof (struct sched), GFP_KERNEL); - if (!s) - return -ENOMEM; - - pr_debug("tx_sched_init\n"); - tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge); - sge->tx_sched = s; - - for (i = 0; i < MAX_NPORTS; i++) { - skb_queue_head_init(&s->p[i].skbq); - t1_sched_update_parms(sge, i, 1500, 1000); - } - - return 0; -} - -/* - * sched_update_avail() computes the delta since the last time it was called - * and updates the per port quota (number of bits that can be sent to the any - * port). - */ -static inline int sched_update_avail(struct sge *sge) -{ - struct sched *s = sge->tx_sched; - ktime_t now = get_clock(); - unsigned int i; - long long delta_time_ns; - - delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated)); - - pr_debug("sched_update_avail delta=%lld\n", delta_time_ns); - if (delta_time_ns < 15000) - return 0; - - for (i = 0; i < MAX_NPORTS; i++) { - struct sched_port *p = &s->p[i]; - unsigned int delta_avail; - - delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13; - p->avail = min(p->avail + delta_avail, s->max_avail); - } - - s->last_updated = now; - - return 1; -} - -/* - * sched_skb() is called from two different places. In the tx path, any - * packet generating load on an output port will call sched_skb() - * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq - * context (skb == NULL). - * The scheduler only returns a skb (which will then be sent) if the - * length of the skb is <= the current quota of the output port. - */ -static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb, - unsigned int credits) -{ - struct sched *s = sge->tx_sched; - struct sk_buff_head *skbq; - unsigned int i, len, update = 1; - - pr_debug("sched_skb %p\n", skb); - if (!skb) { - if (!s->num) - return NULL; - } else { - skbq = &s->p[skb->dev->if_port].skbq; - __skb_queue_tail(skbq, skb); - s->num++; - skb = NULL; - } - - if (credits < MAX_SKB_FRAGS + 1) - goto out; - -again: - for (i = 0; i < MAX_NPORTS; i++) { - s->port = (s->port + 1) & (MAX_NPORTS - 1); - skbq = &s->p[s->port].skbq; - - skb = skb_peek(skbq); - - if (!skb) - continue; - - len = skb->len; - if (len <= s->p[s->port].avail) { - s->p[s->port].avail -= len; - s->num--; - __skb_unlink(skb, skbq); - goto out; - } - skb = NULL; - } - - if (update-- && sched_update_avail(sge)) - goto again; - -out: - /* If there are more pending skbs, we use the hardware to schedule us - * again. - */ - if (s->num && !skb) { - struct cmdQ *q = &sge->cmdQ[0]; - clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); - if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { - set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); - writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); - } - } - pr_debug("sched_skb ret %p\n", skb); - - return skb; -} - -/* - * PIO to indicate that memory mapped Q contains valid descriptor(s). - */ -static inline void doorbell_pio(struct adapter *adapter, u32 val) -{ - wmb(); - writel(val, adapter->regs + A_SG_DOORBELL); -} - -/* - * Frees all RX buffers on the freelist Q. The caller must make sure that - * the SGE is turned off before calling this function. - */ -static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q) -{ - unsigned int cidx = q->cidx; - - while (q->credits--) { - struct freelQ_ce *ce = &q->centries[cidx]; - - pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr), - dma_unmap_len(ce, dma_len), - PCI_DMA_FROMDEVICE); - dev_kfree_skb(ce->skb); - ce->skb = NULL; - if (++cidx == q->size) - cidx = 0; - } -} - -/* - * Free RX free list and response queue resources. - */ -static void free_rx_resources(struct sge *sge) -{ - struct pci_dev *pdev = sge->adapter->pdev; - unsigned int size, i; - - if (sge->respQ.entries) { - size = sizeof(struct respQ_e) * sge->respQ.size; - pci_free_consistent(pdev, size, sge->respQ.entries, - sge->respQ.dma_addr); - } - - for (i = 0; i < SGE_FREELQ_N; i++) { - struct freelQ *q = &sge->freelQ[i]; - - if (q->centries) { - free_freelQ_buffers(pdev, q); - kfree(q->centries); - } - if (q->entries) { - size = sizeof(struct freelQ_e) * q->size; - pci_free_consistent(pdev, size, q->entries, - q->dma_addr); - } - } -} - -/* - * Allocates basic RX resources, consisting of memory mapped freelist Qs and a - * response queue. - */ -static int alloc_rx_resources(struct sge *sge, struct sge_params *p) -{ - struct pci_dev *pdev = sge->adapter->pdev; - unsigned int size, i; - - for (i = 0; i < SGE_FREELQ_N; i++) { - struct freelQ *q = &sge->freelQ[i]; - - q->genbit = 1; - q->size = p->freelQ_size[i]; - q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN; - size = sizeof(struct freelQ_e) * q->size; - q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr); - if (!q->entries) - goto err_no_mem; - - size = sizeof(struct freelQ_ce) * q->size; - q->centries = kzalloc(size, GFP_KERNEL); - if (!q->centries) - goto err_no_mem; - } - - /* - * Calculate the buffer sizes for the two free lists. FL0 accommodates - * regular sized Ethernet frames, FL1 is sized not to exceed 16K, - * including all the sk_buff overhead. - * - * Note: For T2 FL0 and FL1 are reversed. - */ - sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + - sizeof(struct cpl_rx_data) + - sge->freelQ[!sge->jumbo_fl].dma_offset; - - size = (16 * 1024) - - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); - - sge->freelQ[sge->jumbo_fl].rx_buffer_size = size; - - /* - * Setup which skb recycle Q should be used when recycling buffers from - * each free list. - */ - sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0; - sge->freelQ[sge->jumbo_fl].recycleq_idx = 1; - - sge->respQ.genbit = 1; - sge->respQ.size = SGE_RESPQ_E_N; - sge->respQ.credits = 0; - size = sizeof(struct respQ_e) * sge->respQ.size; - sge->respQ.entries = - pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr); - if (!sge->respQ.entries) - goto err_no_mem; - return 0; - -err_no_mem: - free_rx_resources(sge); - return -ENOMEM; -} - -/* - * Reclaims n TX descriptors and frees the buffers associated with them. - */ -static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n) -{ - struct cmdQ_ce *ce; - struct pci_dev *pdev = sge->adapter->pdev; - unsigned int cidx = q->cidx; - - q->in_use -= n; - ce = &q->centries[cidx]; - while (n--) { - if (likely(dma_unmap_len(ce, dma_len))) { - pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr), - dma_unmap_len(ce, dma_len), - PCI_DMA_TODEVICE); - if (q->sop) - q->sop = 0; - } - if (ce->skb) { - dev_kfree_skb_any(ce->skb); - q->sop = 1; - } - ce++; - if (++cidx == q->size) { - cidx = 0; - ce = q->centries; - } - } - q->cidx = cidx; -} - -/* - * Free TX resources. - * - * Assumes that SGE is stopped and all interrupts are disabled. - */ -static void free_tx_resources(struct sge *sge) -{ - struct pci_dev *pdev = sge->adapter->pdev; - unsigned int size, i; - - for (i = 0; i < SGE_CMDQ_N; i++) { - struct cmdQ *q = &sge->cmdQ[i]; - - if (q->centries) { - if (q->in_use) - free_cmdQ_buffers(sge, q, q->in_use); - kfree(q->centries); - } - if (q->entries) { - size = sizeof(struct cmdQ_e) * q->size; - pci_free_consistent(pdev, size, q->entries, - q->dma_addr); - } - } -} - -/* - * Allocates basic TX resources, consisting of memory mapped command Qs. - */ -static int alloc_tx_resources(struct sge *sge, struct sge_params *p) -{ - struct pci_dev *pdev = sge->adapter->pdev; - unsigned int size, i; - - for (i = 0; i < SGE_CMDQ_N; i++) { - struct cmdQ *q = &sge->cmdQ[i]; - - q->genbit = 1; - q->sop = 1; - q->size = p->cmdQ_size[i]; - q->in_use = 0; - q->status = 0; - q->processed = q->cleaned = 0; - q->stop_thres = 0; - spin_lock_init(&q->lock); - size = sizeof(struct cmdQ_e) * q->size; - q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr); - if (!q->entries) - goto err_no_mem; - - size = sizeof(struct cmdQ_ce) * q->size; - q->centries = kzalloc(size, GFP_KERNEL); - if (!q->centries) - goto err_no_mem; - } - - /* - * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE - * only. For queue 0 set the stop threshold so we can handle one more - * packet from each port, plus reserve an additional 24 entries for - * Ethernet packets only. Queue 1 never suspends nor do we reserve - * space for Ethernet packets. - */ - sge->cmdQ[0].stop_thres = sge->adapter->params.nports * - (MAX_SKB_FRAGS + 1); - return 0; - -err_no_mem: - free_tx_resources(sge); - return -ENOMEM; -} - -static inline void setup_ring_params(struct adapter *adapter, u64 addr, - u32 size, int base_reg_lo, - int base_reg_hi, int size_reg) -{ - writel((u32)addr, adapter->regs + base_reg_lo); - writel(addr >> 32, adapter->regs + base_reg_hi); - writel(size, adapter->regs + size_reg); -} - -/* - * Enable/disable VLAN acceleration. - */ -void t1_vlan_mode(struct adapter *adapter, u32 features) -{ - struct sge *sge = adapter->sge; - - if (features & NETIF_F_HW_VLAN_RX) - sge->sge_control |= F_VLAN_XTRACT; - else - sge->sge_control &= ~F_VLAN_XTRACT; - if (adapter->open_device_map) { - writel(sge->sge_control, adapter->regs + A_SG_CONTROL); - readl(adapter->regs + A_SG_CONTROL); /* flush */ - } -} - -/* - * Programs the various SGE registers. However, the engine is not yet enabled, - * but sge->sge_control is setup and ready to go. - */ -static void configure_sge(struct sge *sge, struct sge_params *p) -{ - struct adapter *ap = sge->adapter; - - writel(0, ap->regs + A_SG_CONTROL); - setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size, - A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE); - setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size, - A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE); - setup_ring_params(ap, sge->freelQ[0].dma_addr, - sge->freelQ[0].size, A_SG_FL0BASELWR, - A_SG_FL0BASEUPR, A_SG_FL0SIZE); - setup_ring_params(ap, sge->freelQ[1].dma_addr, - sge->freelQ[1].size, A_SG_FL1BASELWR, - A_SG_FL1BASEUPR, A_SG_FL1SIZE); - - /* The threshold comparison uses <. */ - writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD); - - setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size, - A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE); - writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT); - - sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | - F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | - V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | - V_RX_PKT_OFFSET(sge->rx_pkt_pad); - -#if defined(__BIG_ENDIAN_BITFIELD) - sge->sge_control |= F_ENABLE_BIG_ENDIAN; -#endif - - /* Initialize no-resource timer */ - sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap); - - t1_sge_set_coalesce_params(sge, p); -} - -/* - * Return the payload capacity of the jumbo free-list buffers. - */ -static inline unsigned int jumbo_payload_capacity(const struct sge *sge) -{ - return sge->freelQ[sge->jumbo_fl].rx_buffer_size - - sge->freelQ[sge->jumbo_fl].dma_offset - - sizeof(struct cpl_rx_data); -} - -/* - * Frees all SGE related resources and the sge structure itself - */ -void t1_sge_destroy(struct sge *sge) -{ - int i; - - for_each_port(sge->adapter, i) - free_percpu(sge->port_stats[i]); - - kfree(sge->tx_sched); - free_tx_resources(sge); - free_rx_resources(sge); - kfree(sge); -} - -/* - * Allocates new RX buffers on the freelist Q (and tracks them on the freelist - * context Q) until the Q is full or alloc_skb fails. - * - * It is possible that the generation bits already match, indicating that the - * buffer is already valid and nothing needs to be done. This happens when we - * copied a received buffer into a new sk_buff during the interrupt processing. - * - * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad), - * we specify a RX_OFFSET in order to make sure that the IP header is 4B - * aligned. - */ -static void refill_free_list(struct sge *sge, struct freelQ *q) -{ - struct pci_dev *pdev = sge->adapter->pdev; - struct freelQ_ce *ce = &q->centries[q->pidx]; - struct freelQ_e *e = &q->entries[q->pidx]; - unsigned int dma_len = q->rx_buffer_size - q->dma_offset; - - while (q->credits < q->size) { - struct sk_buff *skb; - dma_addr_t mapping; - - skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC); - if (!skb) - break; - - skb_reserve(skb, q->dma_offset); - mapping = pci_map_single(pdev, skb->data, dma_len, - PCI_DMA_FROMDEVICE); - skb_reserve(skb, sge->rx_pkt_pad); - - ce->skb = skb; - dma_unmap_addr_set(ce, dma_addr, mapping); - dma_unmap_len_set(ce, dma_len, dma_len); - e->addr_lo = (u32)mapping; - e->addr_hi = (u64)mapping >> 32; - e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit); - wmb(); - e->gen2 = V_CMD_GEN2(q->genbit); - - e++; - ce++; - if (++q->pidx == q->size) { - q->pidx = 0; - q->genbit ^= 1; - ce = q->centries; - e = q->entries; - } - q->credits++; - } -} - -/* - * Calls refill_free_list for both free lists. If we cannot fill at least 1/4 - * of both rings, we go into 'few interrupt mode' in order to give the system - * time to free up resources. - */ -static void freelQs_empty(struct sge *sge) -{ - struct adapter *adapter = sge->adapter; - u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE); - u32 irqholdoff_reg; - - refill_free_list(sge, &sge->freelQ[0]); - refill_free_list(sge, &sge->freelQ[1]); - - if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) && - sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) { - irq_reg |= F_FL_EXHAUSTED; - irqholdoff_reg = sge->fixed_intrtimer; - } else { - /* Clear the F_FL_EXHAUSTED interrupts for now */ - irq_reg &= ~F_FL_EXHAUSTED; - irqholdoff_reg = sge->intrtimer_nres; - } - writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER); - writel(irq_reg, adapter->regs + A_SG_INT_ENABLE); - - /* We reenable the Qs to force a freelist GTS interrupt later */ - doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE); -} - -#define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA) -#define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) -#define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \ - F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) - -/* - * Disable SGE Interrupts - */ -void t1_sge_intr_disable(struct sge *sge) -{ - u32 val = readl(sge->adapter->regs + A_PL_ENABLE); - - writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); - writel(0, sge->adapter->regs + A_SG_INT_ENABLE); -} - -/* - * Enable SGE interrupts. - */ -void t1_sge_intr_enable(struct sge *sge) -{ - u32 en = SGE_INT_ENABLE; - u32 val = readl(sge->adapter->regs + A_PL_ENABLE); - - if (sge->adapter->port[0].dev->hw_features & NETIF_F_TSO) - en &= ~F_PACKET_TOO_BIG; - writel(en, sge->adapter->regs + A_SG_INT_ENABLE); - writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); -} - -/* - * Clear SGE interrupts. - */ -void t1_sge_intr_clear(struct sge *sge) -{ - writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE); - writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE); -} - -/* - * SGE 'Error' interrupt handler - */ -int t1_sge_intr_error_handler(struct sge *sge) -{ - struct adapter *adapter = sge->adapter; - u32 cause = readl(adapter->regs + A_SG_INT_CAUSE); - - if (adapter->port[0].dev->hw_features & NETIF_F_TSO) - cause &= ~F_PACKET_TOO_BIG; - if (cause & F_RESPQ_EXHAUSTED) - sge->stats.respQ_empty++; - if (cause & F_RESPQ_OVERFLOW) { - sge->stats.respQ_overflow++; - pr_alert("%s: SGE response queue overflow\n", - adapter->name); - } - if (cause & F_FL_EXHAUSTED) { - sge->stats.freelistQ_empty++; - freelQs_empty(sge); - } - if (cause & F_PACKET_TOO_BIG) { - sge->stats.pkt_too_big++; - pr_alert("%s: SGE max packet size exceeded\n", - adapter->name); - } - if (cause & F_PACKET_MISMATCH) { - sge->stats.pkt_mismatch++; - pr_alert("%s: SGE packet mismatch\n", adapter->name); - } - if (cause & SGE_INT_FATAL) - t1_fatal_err(adapter); - - writel(cause, adapter->regs + A_SG_INT_CAUSE); - return 0; -} - -const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge) -{ - return &sge->stats; -} - -void t1_sge_get_port_stats(const struct sge *sge, int port, - struct sge_port_stats *ss) -{ - int cpu; - - memset(ss, 0, sizeof(*ss)); - for_each_possible_cpu(cpu) { - struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu); - - ss->rx_cso_good += st->rx_cso_good; - ss->tx_cso += st->tx_cso; - ss->tx_tso += st->tx_tso; - ss->tx_need_hdrroom += st->tx_need_hdrroom; - ss->vlan_xtract += st->vlan_xtract; - ss->vlan_insert += st->vlan_insert; - } -} - -/** - * recycle_fl_buf - recycle a free list buffer - * @fl: the free list - * @idx: index of buffer to recycle - * - * Recycles the specified buffer on the given free list by adding it at - * the next available slot on the list. - */ -static void recycle_fl_buf(struct freelQ *fl, int idx) -{ - struct freelQ_e *from = &fl->entries[idx]; - struct freelQ_e *to = &fl->entries[fl->pidx]; - - fl->centries[fl->pidx] = fl->centries[idx]; - to->addr_lo = from->addr_lo; - to->addr_hi = from->addr_hi; - to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit); - wmb(); - to->gen2 = V_CMD_GEN2(fl->genbit); - fl->credits++; - - if (++fl->pidx == fl->size) { - fl->pidx = 0; - fl->genbit ^= 1; - } -} - -static int copybreak __read_mostly = 256; -module_param(copybreak, int, 0); -MODULE_PARM_DESC(copybreak, "Receive copy threshold"); - -/** - * get_packet - return the next ingress packet buffer - * @pdev: the PCI device that received the packet - * @fl: the SGE free list holding the packet - * @len: the actual packet length, excluding any SGE padding - * - * Get the next packet from a free list and complete setup of the - * sk_buff. If the packet is small we make a copy and recycle the - * original buffer, otherwise we use the original buffer itself. If a - * positive drop threshold is supplied packets are dropped and their - * buffers recycled if (a) the number of remaining buffers is under the - * threshold and the packet is too big to copy, or (b) the packet should - * be copied but there is no memory for the copy. - */ -static inline struct sk_buff *get_packet(struct pci_dev *pdev, - struct freelQ *fl, unsigned int len) -{ - struct sk_buff *skb; - const struct freelQ_ce *ce = &fl->centries[fl->cidx]; - - if (len < copybreak) { - skb = alloc_skb(len + 2, GFP_ATOMIC); - if (!skb) - goto use_orig_buf; - - skb_reserve(skb, 2); /* align IP header */ - skb_put(skb, len); - pci_dma_sync_single_for_cpu(pdev, - dma_unmap_addr(ce, dma_addr), - dma_unmap_len(ce, dma_len), - PCI_DMA_FROMDEVICE); - skb_copy_from_linear_data(ce->skb, skb->data, len); - pci_dma_sync_single_for_device(pdev, - dma_unmap_addr(ce, dma_addr), - dma_unmap_len(ce, dma_len), - PCI_DMA_FROMDEVICE); - recycle_fl_buf(fl, fl->cidx); - return skb; - } - -use_orig_buf: - if (fl->credits < 2) { - recycle_fl_buf(fl, fl->cidx); - return NULL; - } - - pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr), - dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); - skb = ce->skb; - prefetch(skb->data); - - skb_put(skb, len); - return skb; -} - -/** - * unexpected_offload - handle an unexpected offload packet - * @adapter: the adapter - * @fl: the free list that received the packet - * - * Called when we receive an unexpected offload packet (e.g., the TOE - * function is disabled or the card is a NIC). Prints a message and - * recycles the buffer. - */ -static void unexpected_offload(struct adapter *adapter, struct freelQ *fl) -{ - struct freelQ_ce *ce = &fl->centries[fl->cidx]; - struct sk_buff *skb = ce->skb; - - pci_dma_sync_single_for_cpu(adapter->pdev, dma_unmap_addr(ce, dma_addr), - dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); - pr_err("%s: unexpected offload packet, cmd %u\n", - adapter->name, *skb->data); - recycle_fl_buf(fl, fl->cidx); -} - -/* - * T1/T2 SGE limits the maximum DMA size per TX descriptor to - * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the - * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner. - * Note that the *_large_page_tx_descs stuff will be optimized out when - * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN. - * - * compute_large_page_descs() computes how many additional descriptors are - * required to break down the stack's request. - */ -static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb) -{ - unsigned int count = 0; - - if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { - unsigned int nfrags = skb_shinfo(skb)->nr_frags; - unsigned int i, len = skb_headlen(skb); - while (len > SGE_TX_DESC_MAX_PLEN) { - count++; - len -= SGE_TX_DESC_MAX_PLEN; - } - for (i = 0; nfrags--; i++) { - skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - len = frag->size; - while (len > SGE_TX_DESC_MAX_PLEN) { - count++; - len -= SGE_TX_DESC_MAX_PLEN; - } - } - } - return count; -} - -/* - * Write a cmdQ entry. - * - * Since this function writes the 'flags' field, it must not be used to - * write the first cmdQ entry. - */ -static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping, - unsigned int len, unsigned int gen, - unsigned int eop) -{ - BUG_ON(len > SGE_TX_DESC_MAX_PLEN); - - e->addr_lo = (u32)mapping; - e->addr_hi = (u64)mapping >> 32; - e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen); - e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen); -} - -/* - * See comment for previous function. - * - * write_tx_descs_large_page() writes additional SGE tx descriptors if - * *desc_len exceeds HW's capability. - */ -static inline unsigned int write_large_page_tx_descs(unsigned int pidx, - struct cmdQ_e **e, - struct cmdQ_ce **ce, - unsigned int *gen, - dma_addr_t *desc_mapping, - unsigned int *desc_len, - unsigned int nfrags, - struct cmdQ *q) -{ - if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { - struct cmdQ_e *e1 = *e; - struct cmdQ_ce *ce1 = *ce; - - while (*desc_len > SGE_TX_DESC_MAX_PLEN) { - *desc_len -= SGE_TX_DESC_MAX_PLEN; - write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN, - *gen, nfrags == 0 && *desc_len == 0); - ce1->skb = NULL; - dma_unmap_len_set(ce1, dma_len, 0); - *desc_mapping += SGE_TX_DESC_MAX_PLEN; - if (*desc_len) { - ce1++; - e1++; - if (++pidx == q->size) { - pidx = 0; - *gen ^= 1; - ce1 = q->centries; - e1 = q->entries; - } - } - } - *e = e1; - *ce = ce1; - } - return pidx; -} - -/* - * Write the command descriptors to transmit the given skb starting at - * descriptor pidx with the given generation. - */ -static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb, - unsigned int pidx, unsigned int gen, - struct cmdQ *q) -{ - dma_addr_t mapping, desc_mapping; - struct cmdQ_e *e, *e1; - struct cmdQ_ce *ce; - unsigned int i, flags, first_desc_len, desc_len, - nfrags = skb_shinfo(skb)->nr_frags; - - e = e1 = &q->entries[pidx]; - ce = &q->centries[pidx]; - - mapping = pci_map_single(adapter->pdev, skb->data, - skb_headlen(skb), PCI_DMA_TODEVICE); - - desc_mapping = mapping; - desc_len = skb_headlen(skb); - - flags = F_CMD_DATAVALID | F_CMD_SOP | - V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) | - V_CMD_GEN2(gen); - first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ? - desc_len : SGE_TX_DESC_MAX_PLEN; - e->addr_lo = (u32)desc_mapping; - e->addr_hi = (u64)desc_mapping >> 32; - e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen); - ce->skb = NULL; - dma_unmap_len_set(ce, dma_len, 0); - - if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN && - desc_len > SGE_TX_DESC_MAX_PLEN) { - desc_mapping += first_desc_len; - desc_len -= first_desc_len; - e1++; - ce++; - if (++pidx == q->size) { - pidx = 0; - gen ^= 1; - e1 = q->entries; - ce = q->centries; - } - pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, - &desc_mapping, &desc_len, - nfrags, q); - - if (likely(desc_len)) - write_tx_desc(e1, desc_mapping, desc_len, gen, - nfrags == 0); - } - - ce->skb = NULL; - dma_unmap_addr_set(ce, dma_addr, mapping); - dma_unmap_len_set(ce, dma_len, skb_headlen(skb)); - - for (i = 0; nfrags--; i++) { - skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - e1++; - ce++; - if (++pidx == q->size) { - pidx = 0; - gen ^= 1; - e1 = q->entries; - ce = q->centries; - } - - mapping = pci_map_page(adapter->pdev, frag->page, - frag->page_offset, frag->size, - PCI_DMA_TODEVICE); - desc_mapping = mapping; - desc_len = frag->size; - - pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, - &desc_mapping, &desc_len, - nfrags, q); - if (likely(desc_len)) - write_tx_desc(e1, desc_mapping, desc_len, gen, - nfrags == 0); - ce->skb = NULL; - dma_unmap_addr_set(ce, dma_addr, mapping); - dma_unmap_len_set(ce, dma_len, frag->size); - } - ce->skb = skb; - wmb(); - e->flags = flags; -} - -/* - * Clean up completed Tx buffers. - */ -static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q) -{ - unsigned int reclaim = q->processed - q->cleaned; - - if (reclaim) { - pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n", - q->processed, q->cleaned); - free_cmdQ_buffers(sge, q, reclaim); - q->cleaned += reclaim; - } -} - -/* - * Called from tasklet. Checks the scheduler for any - * pending skbs that can be sent. - */ -static void restart_sched(unsigned long arg) -{ - struct sge *sge = (struct sge *) arg; - struct adapter *adapter = sge->adapter; - struct cmdQ *q = &sge->cmdQ[0]; - struct sk_buff *skb; - unsigned int credits, queued_skb = 0; - - spin_lock(&q->lock); - reclaim_completed_tx(sge, q); - - credits = q->size - q->in_use; - pr_debug("restart_sched credits=%d\n", credits); - while ((skb = sched_skb(sge, NULL, credits)) != NULL) { - unsigned int genbit, pidx, count; - count = 1 + skb_shinfo(skb)->nr_frags; - count += compute_large_page_tx_descs(skb); - q->in_use += count; - genbit = q->genbit; - pidx = q->pidx; - q->pidx += count; - if (q->pidx >= q->size) { - q->pidx -= q->size; - q->genbit ^= 1; - } - write_tx_descs(adapter, skb, pidx, genbit, q); - credits = q->size - q->in_use; - queued_skb = 1; - } - - if (queued_skb) { - clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); - if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { - set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); - writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); - } - } - spin_unlock(&q->lock); -} - -/** - * sge_rx - process an ingress ethernet packet - * @sge: the sge structure - * @fl: the free list that contains the packet buffer - * @len: the packet length - * - * Process an ingress ethernet pakcet and deliver it to the stack. - */ -static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len) -{ - struct sk_buff *skb; - const struct cpl_rx_pkt *p; - struct adapter *adapter = sge->adapter; - struct sge_port_stats *st; - struct net_device *dev; - - skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad); - if (unlikely(!skb)) { - sge->stats.rx_drops++; - return; - } - - p = (const struct cpl_rx_pkt *) skb->data; - if (p->iff >= adapter->params.nports) { - kfree_skb(skb); - return; - } - __skb_pull(skb, sizeof(*p)); - - st = this_cpu_ptr(sge->port_stats[p->iff]); - dev = adapter->port[p->iff].dev; - - skb->protocol = eth_type_trans(skb, dev); - if ((dev->features & NETIF_F_RXCSUM) && p->csum == 0xffff && - skb->protocol == htons(ETH_P_IP) && - (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) { - ++st->rx_cso_good; - skb->ip_summed = CHECKSUM_UNNECESSARY; - } else - skb_checksum_none_assert(skb); - - if (p->vlan_valid) { - st->vlan_xtract++; - __vlan_hwaccel_put_tag(skb, ntohs(p->vlan)); - } - netif_receive_skb(skb); -} - -/* - * Returns true if a command queue has enough available descriptors that - * we can resume Tx operation after temporarily disabling its packet queue. - */ -static inline int enough_free_Tx_descs(const struct cmdQ *q) -{ - unsigned int r = q->processed - q->cleaned; - - return q->in_use - r < (q->size >> 1); -} - -/* - * Called when sufficient space has become available in the SGE command queues - * after the Tx packet schedulers have been suspended to restart the Tx path. - */ -static void restart_tx_queues(struct sge *sge) -{ - struct adapter *adap = sge->adapter; - int i; - - if (!enough_free_Tx_descs(&sge->cmdQ[0])) - return; - - for_each_port(adap, i) { - struct net_device *nd = adap->port[i].dev; - - if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) && - netif_running(nd)) { - sge->stats.cmdQ_restarted[2]++; - netif_wake_queue(nd); - } - } -} - -/* - * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0 - * information. - */ -static unsigned int update_tx_info(struct adapter *adapter, - unsigned int flags, - unsigned int pr0) -{ - struct sge *sge = adapter->sge; - struct cmdQ *cmdq = &sge->cmdQ[0]; - - cmdq->processed += pr0; - if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) { - freelQs_empty(sge); - flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE); - } - if (flags & F_CMDQ0_ENABLE) { - clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); - - if (cmdq->cleaned + cmdq->in_use != cmdq->processed && - !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { - set_bit(CMDQ_STAT_RUNNING, &cmdq->status); - writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); - } - if (sge->tx_sched) - tasklet_hi_schedule(&sge->tx_sched->sched_tsk); - - flags &= ~F_CMDQ0_ENABLE; - } - - if (unlikely(sge->stopped_tx_queues != 0)) - restart_tx_queues(sge); - - return flags; -} - -/* - * Process SGE responses, up to the supplied budget. Returns the number of - * responses processed. A negative budget is effectively unlimited. - */ -static int process_responses(struct adapter *adapter, int budget) -{ - struct sge *sge = adapter->sge; - struct respQ *q = &sge->respQ; - struct respQ_e *e = &q->entries[q->cidx]; - int done = 0; - unsigned int flags = 0; - unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; - - while (done < budget && e->GenerationBit == q->genbit) { - flags |= e->Qsleeping; - - cmdq_processed[0] += e->Cmdq0CreditReturn; - cmdq_processed[1] += e->Cmdq1CreditReturn; - - /* We batch updates to the TX side to avoid cacheline - * ping-pong of TX state information on MP where the sender - * might run on a different CPU than this function... - */ - if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) { - flags = update_tx_info(adapter, flags, cmdq_processed[0]); - cmdq_processed[0] = 0; - } - - if (unlikely(cmdq_processed[1] > 16)) { - sge->cmdQ[1].processed += cmdq_processed[1]; - cmdq_processed[1] = 0; - } - - if (likely(e->DataValid)) { - struct freelQ *fl = &sge->freelQ[e->FreelistQid]; - - BUG_ON(!e->Sop || !e->Eop); - if (unlikely(e->Offload)) - unexpected_offload(adapter, fl); - else - sge_rx(sge, fl, e->BufferLength); - - ++done; - - /* - * Note: this depends on each packet consuming a - * single free-list buffer; cf. the BUG above. - */ - if (++fl->cidx == fl->size) - fl->cidx = 0; - prefetch(fl->centries[fl->cidx].skb); - - if (unlikely(--fl->credits < - fl->size - SGE_FREEL_REFILL_THRESH)) - refill_free_list(sge, fl); - } else - sge->stats.pure_rsps++; - - e++; - if (unlikely(++q->cidx == q->size)) { - q->cidx = 0; - q->genbit ^= 1; - e = q->entries; - } - prefetch(e); - - if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { - writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); - q->credits = 0; - } - } - - flags = update_tx_info(adapter, flags, cmdq_processed[0]); - sge->cmdQ[1].processed += cmdq_processed[1]; - - return done; -} - -static inline int responses_pending(const struct adapter *adapter) -{ - const struct respQ *Q = &adapter->sge->respQ; - const struct respQ_e *e = &Q->entries[Q->cidx]; - - return e->GenerationBit == Q->genbit; -} - -/* - * A simpler version of process_responses() that handles only pure (i.e., - * non data-carrying) responses. Such respones are too light-weight to justify - * calling a softirq when using NAPI, so we handle them specially in hard - * interrupt context. The function is called with a pointer to a response, - * which the caller must ensure is a valid pure response. Returns 1 if it - * encounters a valid data-carrying response, 0 otherwise. - */ -static int process_pure_responses(struct adapter *adapter) -{ - struct sge *sge = adapter->sge; - struct respQ *q = &sge->respQ; - struct respQ_e *e = &q->entries[q->cidx]; - const struct freelQ *fl = &sge->freelQ[e->FreelistQid]; - unsigned int flags = 0; - unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; - - prefetch(fl->centries[fl->cidx].skb); - if (e->DataValid) - return 1; - - do { - flags |= e->Qsleeping; - - cmdq_processed[0] += e->Cmdq0CreditReturn; - cmdq_processed[1] += e->Cmdq1CreditReturn; - - e++; - if (unlikely(++q->cidx == q->size)) { - q->cidx = 0; - q->genbit ^= 1; - e = q->entries; - } - prefetch(e); - - if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { - writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); - q->credits = 0; - } - sge->stats.pure_rsps++; - } while (e->GenerationBit == q->genbit && !e->DataValid); - - flags = update_tx_info(adapter, flags, cmdq_processed[0]); - sge->cmdQ[1].processed += cmdq_processed[1]; - - return e->GenerationBit == q->genbit; -} - -/* - * Handler for new data events when using NAPI. This does not need any locking - * or protection from interrupts as data interrupts are off at this point and - * other adapter interrupts do not interfere. - */ -int t1_poll(struct napi_struct *napi, int budget) -{ - struct adapter *adapter = container_of(napi, struct adapter, napi); - int work_done = process_responses(adapter, budget); - - if (likely(work_done < budget)) { - napi_complete(napi); - writel(adapter->sge->respQ.cidx, - adapter->regs + A_SG_SLEEPING); - } - return work_done; -} - -irqreturn_t t1_interrupt(int irq, void *data) -{ - struct adapter *adapter = data; - struct sge *sge = adapter->sge; - int handled; - - if (likely(responses_pending(adapter))) { - writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); - - if (napi_schedule_prep(&adapter->napi)) { - if (process_pure_responses(adapter)) - __napi_schedule(&adapter->napi); - else { - /* no data, no NAPI needed */ - writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); - /* undo schedule_prep */ - napi_enable(&adapter->napi); - } - } - return IRQ_HANDLED; - } - - spin_lock(&adapter->async_lock); - handled = t1_slow_intr_handler(adapter); - spin_unlock(&adapter->async_lock); - - if (!handled) - sge->stats.unhandled_irqs++; - - return IRQ_RETVAL(handled != 0); -} - -/* - * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it. - * - * The code figures out how many entries the sk_buff will require in the - * cmdQ and updates the cmdQ data structure with the state once the enqueue - * has complete. Then, it doesn't access the global structure anymore, but - * uses the corresponding fields on the stack. In conjunction with a spinlock - * around that code, we can make the function reentrant without holding the - * lock when we actually enqueue (which might be expensive, especially on - * architectures with IO MMUs). - * - * This runs with softirqs disabled. - */ -static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter, - unsigned int qid, struct net_device *dev) -{ - struct sge *sge = adapter->sge; - struct cmdQ *q = &sge->cmdQ[qid]; - unsigned int credits, pidx, genbit, count, use_sched_skb = 0; - - if (!spin_trylock(&q->lock)) - return NETDEV_TX_LOCKED; - - reclaim_completed_tx(sge, q); - - pidx = q->pidx; - credits = q->size - q->in_use; - count = 1 + skb_shinfo(skb)->nr_frags; - count += compute_large_page_tx_descs(skb); - - /* Ethernet packet */ - if (unlikely(credits < count)) { - if (!netif_queue_stopped(dev)) { - netif_stop_queue(dev); - set_bit(dev->if_port, &sge->stopped_tx_queues); - sge->stats.cmdQ_full[2]++; - pr_err("%s: Tx ring full while queue awake!\n", - adapter->name); - } - spin_unlock(&q->lock); - return NETDEV_TX_BUSY; - } - - if (unlikely(credits - count < q->stop_thres)) { - netif_stop_queue(dev); - set_bit(dev->if_port, &sge->stopped_tx_queues); - sge->stats.cmdQ_full[2]++; - } - - /* T204 cmdQ0 skbs that are destined for a certain port have to go - * through the scheduler. - */ - if (sge->tx_sched && !qid && skb->dev) { -use_sched: - use_sched_skb = 1; - /* Note that the scheduler might return a different skb than - * the one passed in. - */ - skb = sched_skb(sge, skb, credits); - if (!skb) { - spin_unlock(&q->lock); - return NETDEV_TX_OK; - } - pidx = q->pidx; - count = 1 + skb_shinfo(skb)->nr_frags; - count += compute_large_page_tx_descs(skb); - } - - q->in_use += count; - genbit = q->genbit; - pidx = q->pidx; - q->pidx += count; - if (q->pidx >= q->size) { - q->pidx -= q->size; - q->genbit ^= 1; - } - spin_unlock(&q->lock); - - write_tx_descs(adapter, skb, pidx, genbit, q); - - /* - * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring - * the doorbell if the Q is asleep. There is a natural race, where - * the hardware is going to sleep just after we checked, however, - * then the interrupt handler will detect the outstanding TX packet - * and ring the doorbell for us. - */ - if (qid) - doorbell_pio(adapter, F_CMDQ1_ENABLE); - else { - clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); - if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { - set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); - writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); - } - } - - if (use_sched_skb) { - if (spin_trylock(&q->lock)) { - credits = q->size - q->in_use; - skb = NULL; - goto use_sched; - } - } - return NETDEV_TX_OK; -} - -#define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14)) - -/* - * eth_hdr_len - return the length of an Ethernet header - * @data: pointer to the start of the Ethernet header - * - * Returns the length of an Ethernet header, including optional VLAN tag. - */ -static inline int eth_hdr_len(const void *data) -{ - const struct ethhdr *e = data; - - return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN; -} - -/* - * Adds the CPL header to the sk_buff and passes it to t1_sge_tx. - */ -netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct adapter *adapter = dev->ml_priv; - struct sge *sge = adapter->sge; - struct sge_port_stats *st = this_cpu_ptr(sge->port_stats[dev->if_port]); - struct cpl_tx_pkt *cpl; - struct sk_buff *orig_skb = skb; - int ret; - - if (skb->protocol == htons(ETH_P_CPL5)) - goto send; - - /* - * We are using a non-standard hard_header_len. - * Allocate more header room in the rare cases it is not big enough. - */ - if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) { - skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso)); - ++st->tx_need_hdrroom; - dev_kfree_skb_any(orig_skb); - if (!skb) - return NETDEV_TX_OK; - } - - if (skb_shinfo(skb)->gso_size) { - int eth_type; - struct cpl_tx_pkt_lso *hdr; - - ++st->tx_tso; - - eth_type = skb_network_offset(skb) == ETH_HLEN ? - CPL_ETH_II : CPL_ETH_II_VLAN; - - hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr)); - hdr->opcode = CPL_TX_PKT_LSO; - hdr->ip_csum_dis = hdr->l4_csum_dis = 0; - hdr->ip_hdr_words = ip_hdr(skb)->ihl; - hdr->tcp_hdr_words = tcp_hdr(skb)->doff; - hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, - skb_shinfo(skb)->gso_size)); - hdr->len = htonl(skb->len - sizeof(*hdr)); - cpl = (struct cpl_tx_pkt *)hdr; - } else { - /* - * Packets shorter than ETH_HLEN can break the MAC, drop them - * early. Also, we may get oversized packets because some - * parts of the kernel don't handle our unusual hard_header_len - * right, drop those too. - */ - if (unlikely(skb->len < ETH_HLEN || - skb->len > dev->mtu + eth_hdr_len(skb->data))) { - pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name, - skb->len, eth_hdr_len(skb->data), dev->mtu); - dev_kfree_skb_any(skb); - return NETDEV_TX_OK; - } - - if (skb->ip_summed == CHECKSUM_PARTIAL && - ip_hdr(skb)->protocol == IPPROTO_UDP) { - if (unlikely(skb_checksum_help(skb))) { - pr_debug("%s: unable to do udp checksum\n", dev->name); - dev_kfree_skb_any(skb); - return NETDEV_TX_OK; - } - } - - /* Hmmm, assuming to catch the gratious arp... and we'll use - * it to flush out stuck espi packets... - */ - if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) { - if (skb->protocol == htons(ETH_P_ARP) && - arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) { - adapter->sge->espibug_skb[dev->if_port] = skb; - /* We want to re-use this skb later. We - * simply bump the reference count and it - * will not be freed... - */ - skb = skb_get(skb); - } - } - - cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl)); - cpl->opcode = CPL_TX_PKT; - cpl->ip_csum_dis = 1; /* SW calculates IP csum */ - cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1; - /* the length field isn't used so don't bother setting it */ - - st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL); - } - cpl->iff = dev->if_port; - - if (vlan_tx_tag_present(skb)) { - cpl->vlan_valid = 1; - cpl->vlan = htons(vlan_tx_tag_get(skb)); - st->vlan_insert++; - } else - cpl->vlan_valid = 0; - -send: - ret = t1_sge_tx(skb, adapter, 0, dev); - - /* If transmit busy, and we reallocated skb's due to headroom limit, - * then silently discard to avoid leak. - */ - if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) { - dev_kfree_skb_any(skb); - ret = NETDEV_TX_OK; - } - return ret; -} - -/* - * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled. - */ -static void sge_tx_reclaim_cb(unsigned long data) -{ - int i; - struct sge *sge = (struct sge *)data; - - for (i = 0; i < SGE_CMDQ_N; ++i) { - struct cmdQ *q = &sge->cmdQ[i]; - - if (!spin_trylock(&q->lock)) - continue; - - reclaim_completed_tx(sge, q); - if (i == 0 && q->in_use) { /* flush pending credits */ - writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); - } - spin_unlock(&q->lock); - } - mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); -} - -/* - * Propagate changes of the SGE coalescing parameters to the HW. - */ -int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p) -{ - sge->fixed_intrtimer = p->rx_coalesce_usecs * - core_ticks_per_usec(sge->adapter); - writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER); - return 0; -} - -/* - * Allocates both RX and TX resources and configures the SGE. However, - * the hardware is not enabled yet. - */ -int t1_sge_configure(struct sge *sge, struct sge_params *p) -{ - if (alloc_rx_resources(sge, p)) - return -ENOMEM; - if (alloc_tx_resources(sge, p)) { - free_rx_resources(sge); - return -ENOMEM; - } - configure_sge(sge, p); - - /* - * Now that we have sized the free lists calculate the payload - * capacity of the large buffers. Other parts of the driver use - * this to set the max offload coalescing size so that RX packets - * do not overflow our large buffers. - */ - p->large_buf_capacity = jumbo_payload_capacity(sge); - return 0; -} - -/* - * Disables the DMA engine. - */ -void t1_sge_stop(struct sge *sge) -{ - int i; - writel(0, sge->adapter->regs + A_SG_CONTROL); - readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ - - if (is_T2(sge->adapter)) - del_timer_sync(&sge->espibug_timer); - - del_timer_sync(&sge->tx_reclaim_timer); - if (sge->tx_sched) - tx_sched_stop(sge); - - for (i = 0; i < MAX_NPORTS; i++) - kfree_skb(sge->espibug_skb[i]); -} - -/* - * Enables the DMA engine. - */ -void t1_sge_start(struct sge *sge) -{ - refill_free_list(sge, &sge->freelQ[0]); - refill_free_list(sge, &sge->freelQ[1]); - - writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); - doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); - readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ - - mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); - - if (is_T2(sge->adapter)) - mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); -} - -/* - * Callback for the T2 ESPI 'stuck packet feature' workaorund - */ -static void espibug_workaround_t204(unsigned long data) -{ - struct adapter *adapter = (struct adapter *)data; - struct sge *sge = adapter->sge; - unsigned int nports = adapter->params.nports; - u32 seop[MAX_NPORTS]; - - if (adapter->open_device_map & PORT_MASK) { - int i; - - if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0) - return; - - for (i = 0; i < nports; i++) { - struct sk_buff *skb = sge->espibug_skb[i]; - - if (!netif_running(adapter->port[i].dev) || - netif_queue_stopped(adapter->port[i].dev) || - !seop[i] || ((seop[i] & 0xfff) != 0) || !skb) - continue; - - if (!skb->cb[0]) { - skb_copy_to_linear_data_offset(skb, - sizeof(struct cpl_tx_pkt), - ch_mac_addr, - ETH_ALEN); - skb_copy_to_linear_data_offset(skb, - skb->len - 10, - ch_mac_addr, - ETH_ALEN); - skb->cb[0] = 0xff; - } - - /* bump the reference count to avoid freeing of - * the skb once the DMA has completed. - */ - skb = skb_get(skb); - t1_sge_tx(skb, adapter, 0, adapter->port[i].dev); - } - } - mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); -} - -static void espibug_workaround(unsigned long data) -{ - struct adapter *adapter = (struct adapter *)data; - struct sge *sge = adapter->sge; - - if (netif_running(adapter->port[0].dev)) { - struct sk_buff *skb = sge->espibug_skb[0]; - u32 seop = t1_espi_get_mon(adapter, 0x930, 0); - - if ((seop & 0xfff0fff) == 0xfff && skb) { - if (!skb->cb[0]) { - skb_copy_to_linear_data_offset(skb, - sizeof(struct cpl_tx_pkt), - ch_mac_addr, - ETH_ALEN); - skb_copy_to_linear_data_offset(skb, - skb->len - 10, - ch_mac_addr, - ETH_ALEN); - skb->cb[0] = 0xff; - } - - /* bump the reference count to avoid freeing of the - * skb once the DMA has completed. - */ - skb = skb_get(skb); - t1_sge_tx(skb, adapter, 0, adapter->port[0].dev); - } - } - mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); -} - -/* - * Creates a t1_sge structure and returns suggested resource parameters. - */ -struct sge * __devinit t1_sge_create(struct adapter *adapter, - struct sge_params *p) -{ - struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL); - int i; - - if (!sge) - return NULL; - - sge->adapter = adapter; - sge->netdev = adapter->port[0].dev; - sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2; - sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; - - for_each_port(adapter, i) { - sge->port_stats[i] = alloc_percpu(struct sge_port_stats); - if (!sge->port_stats[i]) - goto nomem_port; - } - - init_timer(&sge->tx_reclaim_timer); - sge->tx_reclaim_timer.data = (unsigned long)sge; - sge->tx_reclaim_timer.function = sge_tx_reclaim_cb; - - if (is_T2(sge->adapter)) { - init_timer(&sge->espibug_timer); - - if (adapter->params.nports > 1) { - tx_sched_init(sge); - sge->espibug_timer.function = espibug_workaround_t204; - } else - sge->espibug_timer.function = espibug_workaround; - sge->espibug_timer.data = (unsigned long)sge->adapter; - - sge->espibug_timeout = 1; - /* for T204, every 10ms */ - if (adapter->params.nports > 1) - sge->espibug_timeout = HZ/100; - } - - - p->cmdQ_size[0] = SGE_CMDQ0_E_N; - p->cmdQ_size[1] = SGE_CMDQ1_E_N; - p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; - p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; - if (sge->tx_sched) { - if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) - p->rx_coalesce_usecs = 15; - else - p->rx_coalesce_usecs = 50; - } else - p->rx_coalesce_usecs = 50; - - p->coalesce_enable = 0; - p->sample_interval_usecs = 0; - - return sge; -nomem_port: - while (i >= 0) { - free_percpu(sge->port_stats[i]); - --i; - } - kfree(sge); - return NULL; - -} diff --git a/drivers/net/chelsio/sge.h b/drivers/net/chelsio/sge.h deleted file mode 100644 index e03980bcdd6..00000000000 --- a/drivers/net/chelsio/sge.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************** - * * - * File: sge.h * - * $Revision: 1.11 $ * - * $Date: 2005/06/21 22:10:55 $ * - * Description: * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#ifndef _CXGB_SGE_H_ -#define _CXGB_SGE_H_ - -#include <linux/types.h> -#include <linux/interrupt.h> -#include <asm/byteorder.h> - -struct sge_intr_counts { - unsigned int rx_drops; /* # of packets dropped due to no mem */ - unsigned int pure_rsps; /* # of non-payload responses */ - unsigned int unhandled_irqs; /* # of unhandled interrupts */ - unsigned int respQ_empty; /* # times respQ empty */ - unsigned int respQ_overflow; /* # respQ overflow (fatal) */ - unsigned int freelistQ_empty; /* # times freelist empty */ - unsigned int pkt_too_big; /* packet too large (fatal) */ - unsigned int pkt_mismatch; - unsigned int cmdQ_full[3]; /* not HW IRQ, host cmdQ[] full */ - unsigned int cmdQ_restarted[3];/* # of times cmdQ X was restarted */ -}; - -struct sge_port_stats { - u64 rx_cso_good; /* # of successful RX csum offloads */ - u64 tx_cso; /* # of TX checksum offloads */ - u64 tx_tso; /* # of TSO requests */ - u64 vlan_xtract; /* # of VLAN tag extractions */ - u64 vlan_insert; /* # of VLAN tag insertions */ - u64 tx_need_hdrroom; /* # of TX skbs in need of more header room */ -}; - -struct sk_buff; -struct net_device; -struct adapter; -struct sge_params; -struct sge; - -struct sge *t1_sge_create(struct adapter *, struct sge_params *); -int t1_sge_configure(struct sge *, struct sge_params *); -int t1_sge_set_coalesce_params(struct sge *, struct sge_params *); -void t1_sge_destroy(struct sge *); -irqreturn_t t1_interrupt(int irq, void *cookie); -int t1_poll(struct napi_struct *, int); - -netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev); -void t1_vlan_mode(struct adapter *adapter, u32 features); -void t1_sge_start(struct sge *); -void t1_sge_stop(struct sge *); -int t1_sge_intr_error_handler(struct sge *); -void t1_sge_intr_enable(struct sge *); -void t1_sge_intr_disable(struct sge *); -void t1_sge_intr_clear(struct sge *); -const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge); -void t1_sge_get_port_stats(const struct sge *sge, int port, struct sge_port_stats *); -unsigned int t1_sched_update_parms(struct sge *, unsigned int, unsigned int, - unsigned int); - -#endif /* _CXGB_SGE_H_ */ diff --git a/drivers/net/chelsio/subr.c b/drivers/net/chelsio/subr.c deleted file mode 100644 index 8a43c7e1970..00000000000 --- a/drivers/net/chelsio/subr.c +++ /dev/null @@ -1,1130 +0,0 @@ -/***************************************************************************** - * * - * File: subr.c * - * $Revision: 1.27 $ * - * $Date: 2005/06/22 01:08:36 $ * - * Description: * - * Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * - * All rights reserved. * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: Dimitrios Michailidis <dm@chelsio.com> * - * Tina Yang <tainay@chelsio.com> * - * Felix Marti <felix@chelsio.com> * - * Scott Bardone <sbardone@chelsio.com> * - * Kurt Ottaway <kottaway@chelsio.com> * - * Frank DiMambro <frank@chelsio.com> * - * * - * History: * - * * - ****************************************************************************/ - -#include "common.h" -#include "elmer0.h" -#include "regs.h" -#include "gmac.h" -#include "cphy.h" -#include "sge.h" -#include "tp.h" -#include "espi.h" - -/** - * t1_wait_op_done - wait until an operation is completed - * @adapter: the adapter performing the operation - * @reg: the register to check for completion - * @mask: a single-bit field within @reg that indicates completion - * @polarity: the value of the field when the operation is completed - * @attempts: number of check iterations - * @delay: delay in usecs between iterations - * - * Wait until an operation is completed by checking a bit in a register - * up to @attempts times. Returns %0 if the operation completes and %1 - * otherwise. - */ -static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, - int attempts, int delay) -{ - while (1) { - u32 val = readl(adapter->regs + reg) & mask; - - if (!!val == polarity) - return 0; - if (--attempts == 0) - return 1; - if (delay) - udelay(delay); - } -} - -#define TPI_ATTEMPTS 50 - -/* - * Write a register over the TPI interface (unlocked and locked versions). - */ -int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value) -{ - int tpi_busy; - - writel(addr, adapter->regs + A_TPI_ADDR); - writel(value, adapter->regs + A_TPI_WR_DATA); - writel(F_TPIWR, adapter->regs + A_TPI_CSR); - - tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1, - TPI_ATTEMPTS, 3); - if (tpi_busy) - pr_alert("%s: TPI write to 0x%x failed\n", - adapter->name, addr); - return tpi_busy; -} - -int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value) -{ - int ret; - - spin_lock(&adapter->tpi_lock); - ret = __t1_tpi_write(adapter, addr, value); - spin_unlock(&adapter->tpi_lock); - return ret; -} - -/* - * Read a register over the TPI interface (unlocked and locked versions). - */ -int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp) -{ - int tpi_busy; - - writel(addr, adapter->regs + A_TPI_ADDR); - writel(0, adapter->regs + A_TPI_CSR); - - tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1, - TPI_ATTEMPTS, 3); - if (tpi_busy) - pr_alert("%s: TPI read from 0x%x failed\n", - adapter->name, addr); - else - *valp = readl(adapter->regs + A_TPI_RD_DATA); - return tpi_busy; -} - -int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp) -{ - int ret; - - spin_lock(&adapter->tpi_lock); - ret = __t1_tpi_read(adapter, addr, valp); - spin_unlock(&adapter->tpi_lock); - return ret; -} - -/* - * Set a TPI parameter. - */ -static void t1_tpi_par(adapter_t *adapter, u32 value) -{ - writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR); -} - -/* - * Called when a port's link settings change to propagate the new values to the - * associated PHY and MAC. After performing the common tasks it invokes an - * OS-specific handler. - */ -void t1_link_changed(adapter_t *adapter, int port_id) -{ - int link_ok, speed, duplex, fc; - struct cphy *phy = adapter->port[port_id].phy; - struct link_config *lc = &adapter->port[port_id].link_config; - - phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc); - - lc->speed = speed < 0 ? SPEED_INVALID : speed; - lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex; - if (!(lc->requested_fc & PAUSE_AUTONEG)) - fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); - - if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) { - /* Set MAC speed, duplex, and flow control to match PHY. */ - struct cmac *mac = adapter->port[port_id].mac; - - mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc); - lc->fc = (unsigned char)fc; - } - t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc); -} - -static int t1_pci_intr_handler(adapter_t *adapter) -{ - u32 pcix_cause; - - pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause); - - if (pcix_cause) { - pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, - pcix_cause); - t1_fatal_err(adapter); /* PCI errors are fatal */ - } - return 0; -} - -#ifdef CONFIG_CHELSIO_T1_1G -#include "fpga_defs.h" - -/* - * PHY interrupt handler for FPGA boards. - */ -static int fpga_phy_intr_handler(adapter_t *adapter) -{ - int p; - u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE); - - for_each_port(adapter, p) - if (cause & (1 << p)) { - struct cphy *phy = adapter->port[p].phy; - int phy_cause = phy->ops->interrupt_handler(phy); - - if (phy_cause & cphy_cause_link_change) - t1_link_changed(adapter, p); - } - writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE); - return 0; -} - -/* - * Slow path interrupt handler for FPGAs. - */ -static int fpga_slow_intr(adapter_t *adapter) -{ - u32 cause = readl(adapter->regs + A_PL_CAUSE); - - cause &= ~F_PL_INTR_SGE_DATA; - if (cause & F_PL_INTR_SGE_ERR) - t1_sge_intr_error_handler(adapter->sge); - - if (cause & FPGA_PCIX_INTERRUPT_GMAC) - fpga_phy_intr_handler(adapter); - - if (cause & FPGA_PCIX_INTERRUPT_TP) { - /* - * FPGA doesn't support MC4 interrupts and it requires - * this odd layer of indirection for MC5. - */ - u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); - - /* Clear TP interrupt */ - writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); - } - if (cause & FPGA_PCIX_INTERRUPT_PCIX) - t1_pci_intr_handler(adapter); - - /* Clear the interrupts just processed. */ - if (cause) - writel(cause, adapter->regs + A_PL_CAUSE); - - return cause != 0; -} -#endif - -/* - * Wait until Elmer's MI1 interface is ready for new operations. - */ -static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg) -{ - int attempts = 100, busy; - - do { - u32 val; - - __t1_tpi_read(adapter, mi1_reg, &val); - busy = val & F_MI1_OP_BUSY; - if (busy) - udelay(10); - } while (busy && --attempts); - if (busy) - pr_alert("%s: MDIO operation timed out\n", adapter->name); - return busy; -} - -/* - * MI1 MDIO initialization. - */ -static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi) -{ - u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1; - u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) | - V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv); - - if (!(bi->caps & SUPPORTED_10000baseT_Full)) - val |= V_MI1_SOF(1); - t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val); -} - -#if defined(CONFIG_CHELSIO_T1_1G) -/* - * Elmer MI1 MDIO read/write operations. - */ -static int mi1_mdio_read(struct net_device *dev, int phy_addr, int mmd_addr, - u16 reg_addr) -{ - struct adapter *adapter = dev->ml_priv; - u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); - unsigned int val; - - spin_lock(&adapter->tpi_lock); - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); - __t1_tpi_write(adapter, - A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ); - mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); - __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val); - spin_unlock(&adapter->tpi_lock); - return val; -} - -static int mi1_mdio_write(struct net_device *dev, int phy_addr, int mmd_addr, - u16 reg_addr, u16 val) -{ - struct adapter *adapter = dev->ml_priv; - u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); - - spin_lock(&adapter->tpi_lock); - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val); - __t1_tpi_write(adapter, - A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE); - mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); - spin_unlock(&adapter->tpi_lock); - return 0; -} - -static const struct mdio_ops mi1_mdio_ops = { - .init = mi1_mdio_init, - .read = mi1_mdio_read, - .write = mi1_mdio_write, - .mode_support = MDIO_SUPPORTS_C22 -}; - -#endif - -static int mi1_mdio_ext_read(struct net_device *dev, int phy_addr, int mmd_addr, - u16 reg_addr) -{ - struct adapter *adapter = dev->ml_priv; - u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr); - unsigned int val; - - spin_lock(&adapter->tpi_lock); - - /* Write the address we want. */ - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr); - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, - MI1_OP_INDIRECT_ADDRESS); - mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); - - /* Write the operation we want. */ - __t1_tpi_write(adapter, - A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ); - mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); - - /* Read the data. */ - __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val); - spin_unlock(&adapter->tpi_lock); - return val; -} - -static int mi1_mdio_ext_write(struct net_device *dev, int phy_addr, - int mmd_addr, u16 reg_addr, u16 val) -{ - struct adapter *adapter = dev->ml_priv; - u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr); - - spin_lock(&adapter->tpi_lock); - - /* Write the address we want. */ - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr); - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, - MI1_OP_INDIRECT_ADDRESS); - mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); - - /* Write the data. */ - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val); - __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE); - mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); - spin_unlock(&adapter->tpi_lock); - return 0; -} - -static const struct mdio_ops mi1_mdio_ext_ops = { - .init = mi1_mdio_init, - .read = mi1_mdio_ext_read, - .write = mi1_mdio_ext_write, - .mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22 -}; - -enum { - CH_BRD_T110_1CU, - CH_BRD_N110_1F, - CH_BRD_N210_1F, - CH_BRD_T210_1F, - CH_BRD_T210_1CU, - CH_BRD_N204_4CU, -}; - -static const struct board_info t1_board[] = { - { - .board = CHBT_BOARD_CHT110, - .port_number = 1, - .caps = SUPPORTED_10000baseT_Full, - .chip_term = CHBT_TERM_T1, - .chip_mac = CHBT_MAC_PM3393, - .chip_phy = CHBT_PHY_MY3126, - .clock_core = 125000000, - .clock_mc3 = 150000000, - .clock_mc4 = 125000000, - .espi_nports = 1, - .clock_elmer0 = 44, - .mdio_mdien = 1, - .mdio_mdiinv = 1, - .mdio_mdc = 1, - .mdio_phybaseaddr = 1, - .gmac = &t1_pm3393_ops, - .gphy = &t1_my3126_ops, - .mdio_ops = &mi1_mdio_ext_ops, - .desc = "Chelsio T110 1x10GBase-CX4 TOE", - }, - - { - .board = CHBT_BOARD_N110, - .port_number = 1, - .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE, - .chip_term = CHBT_TERM_T1, - .chip_mac = CHBT_MAC_PM3393, - .chip_phy = CHBT_PHY_88X2010, - .clock_core = 125000000, - .espi_nports = 1, - .clock_elmer0 = 44, - .mdio_mdien = 0, - .mdio_mdiinv = 0, - .mdio_mdc = 1, - .mdio_phybaseaddr = 0, - .gmac = &t1_pm3393_ops, - .gphy = &t1_mv88x201x_ops, - .mdio_ops = &mi1_mdio_ext_ops, - .desc = "Chelsio N110 1x10GBaseX NIC", - }, - - { - .board = CHBT_BOARD_N210, - .port_number = 1, - .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE, - .chip_term = CHBT_TERM_T2, - .chip_mac = CHBT_MAC_PM3393, - .chip_phy = CHBT_PHY_88X2010, - .clock_core = 125000000, - .espi_nports = 1, - .clock_elmer0 = 44, - .mdio_mdien = 0, - .mdio_mdiinv = 0, - .mdio_mdc = 1, - .mdio_phybaseaddr = 0, - .gmac = &t1_pm3393_ops, - .gphy = &t1_mv88x201x_ops, - .mdio_ops = &mi1_mdio_ext_ops, - .desc = "Chelsio N210 1x10GBaseX NIC", - }, - - { - .board = CHBT_BOARD_CHT210, - .port_number = 1, - .caps = SUPPORTED_10000baseT_Full, - .chip_term = CHBT_TERM_T2, - .chip_mac = CHBT_MAC_PM3393, - .chip_phy = CHBT_PHY_88X2010, - .clock_core = 125000000, - .clock_mc3 = 133000000, - .clock_mc4 = 125000000, - .espi_nports = 1, - .clock_elmer0 = 44, - .mdio_mdien = 0, - .mdio_mdiinv = 0, - .mdio_mdc = 1, - .mdio_phybaseaddr = 0, - .gmac = &t1_pm3393_ops, - .gphy = &t1_mv88x201x_ops, - .mdio_ops = &mi1_mdio_ext_ops, - .desc = "Chelsio T210 1x10GBaseX TOE", - }, - - { - .board = CHBT_BOARD_CHT210, - .port_number = 1, - .caps = SUPPORTED_10000baseT_Full, - .chip_term = CHBT_TERM_T2, - .chip_mac = CHBT_MAC_PM3393, - .chip_phy = CHBT_PHY_MY3126, - .clock_core = 125000000, - .clock_mc3 = 133000000, - .clock_mc4 = 125000000, - .espi_nports = 1, - .clock_elmer0 = 44, - .mdio_mdien = 1, - .mdio_mdiinv = 1, - .mdio_mdc = 1, - .mdio_phybaseaddr = 1, - .gmac = &t1_pm3393_ops, - .gphy = &t1_my3126_ops, - .mdio_ops = &mi1_mdio_ext_ops, - .desc = "Chelsio T210 1x10GBase-CX4 TOE", - }, - -#ifdef CONFIG_CHELSIO_T1_1G - { - .board = CHBT_BOARD_CHN204, - .port_number = 4, - .caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full - | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full - | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | - SUPPORTED_PAUSE | SUPPORTED_TP, - .chip_term = CHBT_TERM_T2, - .chip_mac = CHBT_MAC_VSC7321, - .chip_phy = CHBT_PHY_88E1111, - .clock_core = 100000000, - .espi_nports = 4, - .clock_elmer0 = 44, - .mdio_mdien = 0, - .mdio_mdiinv = 0, - .mdio_mdc = 0, - .mdio_phybaseaddr = 4, - .gmac = &t1_vsc7326_ops, - .gphy = &t1_mv88e1xxx_ops, - .mdio_ops = &mi1_mdio_ops, - .desc = "Chelsio N204 4x100/1000BaseT NIC", - }, -#endif - -}; - -DEFINE_PCI_DEVICE_TABLE(t1_pci_tbl) = { - CH_DEVICE(8, 0, CH_BRD_T110_1CU), - CH_DEVICE(8, 1, CH_BRD_T110_1CU), - CH_DEVICE(7, 0, CH_BRD_N110_1F), - CH_DEVICE(10, 1, CH_BRD_N210_1F), - CH_DEVICE(11, 1, CH_BRD_T210_1F), - CH_DEVICE(14, 1, CH_BRD_T210_1CU), - CH_DEVICE(16, 1, CH_BRD_N204_4CU), - { 0 } -}; - -MODULE_DEVICE_TABLE(pci, t1_pci_tbl); - -/* - * Return the board_info structure with a given index. Out-of-range indices - * return NULL. - */ -const struct board_info *t1_get_board_info(unsigned int board_id) -{ - return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL; -} - -struct chelsio_vpd_t { - u32 format_version; - u8 serial_number[16]; - u8 mac_base_address[6]; - u8 pad[2]; /* make multiple-of-4 size requirement explicit */ -}; - -#define EEPROMSIZE (8 * 1024) -#define EEPROM_MAX_POLL 4 - -/* - * Read SEEPROM. A zero is written to the flag register when the address is - * written to the Control register. The hardware device will set the flag to a - * one when 4B have been transferred to the Data register. - */ -int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data) -{ - int i = EEPROM_MAX_POLL; - u16 val; - u32 v; - - if (addr >= EEPROMSIZE || (addr & 3)) - return -EINVAL; - - pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr); - do { - udelay(50); - pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val); - } while (!(val & F_VPD_OP_FLAG) && --i); - - if (!(val & F_VPD_OP_FLAG)) { - pr_err("%s: reading EEPROM address 0x%x failed\n", - adapter->name, addr); - return -EIO; - } - pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v); - *data = cpu_to_le32(v); - return 0; -} - -static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd) -{ - int addr, ret = 0; - - for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32)) - ret = t1_seeprom_read(adapter, addr, - (__le32 *)((u8 *)vpd + addr)); - - return ret; -} - -/* - * Read a port's MAC address from the VPD ROM. - */ -static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[]) -{ - struct chelsio_vpd_t vpd; - - if (t1_eeprom_vpd_get(adapter, &vpd)) - return 1; - memcpy(mac_addr, vpd.mac_base_address, 5); - mac_addr[5] = vpd.mac_base_address[5] + index; - return 0; -} - -/* - * Set up the MAC/PHY according to the requested link settings. - * - * If the PHY can auto-negotiate first decide what to advertise, then - * enable/disable auto-negotiation as desired and reset. - * - * If the PHY does not auto-negotiate we just reset it. - * - * If auto-negotiation is off set the MAC to the proper speed/duplex/FC, - * otherwise do it later based on the outcome of auto-negotiation. - */ -int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc) -{ - unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); - - if (lc->supported & SUPPORTED_Autoneg) { - lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE); - if (fc) { - if (fc == ((PAUSE_RX | PAUSE_TX) & - (mac->adapter->params.nports < 2))) - lc->advertising |= ADVERTISED_PAUSE; - else { - lc->advertising |= ADVERTISED_ASYM_PAUSE; - if (fc == PAUSE_RX) - lc->advertising |= ADVERTISED_PAUSE; - } - } - phy->ops->advertise(phy, lc->advertising); - - if (lc->autoneg == AUTONEG_DISABLE) { - lc->speed = lc->requested_speed; - lc->duplex = lc->requested_duplex; - lc->fc = (unsigned char)fc; - mac->ops->set_speed_duplex_fc(mac, lc->speed, - lc->duplex, fc); - /* Also disables autoneg */ - phy->state = PHY_AUTONEG_RDY; - phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex); - phy->ops->reset(phy, 0); - } else { - phy->state = PHY_AUTONEG_EN; - phy->ops->autoneg_enable(phy); /* also resets PHY */ - } - } else { - phy->state = PHY_AUTONEG_RDY; - mac->ops->set_speed_duplex_fc(mac, -1, -1, fc); - lc->fc = (unsigned char)fc; - phy->ops->reset(phy, 0); - } - return 0; -} - -/* - * External interrupt handler for boards using elmer0. - */ -int t1_elmer0_ext_intr_handler(adapter_t *adapter) -{ - struct cphy *phy; - int phy_cause; - u32 cause; - - t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause); - - switch (board_info(adapter)->board) { -#ifdef CONFIG_CHELSIO_T1_1G - case CHBT_BOARD_CHT204: - case CHBT_BOARD_CHT204E: - case CHBT_BOARD_CHN204: - case CHBT_BOARD_CHT204V: { - int i, port_bit; - for_each_port(adapter, i) { - port_bit = i + 1; - if (!(cause & (1 << port_bit))) - continue; - - phy = adapter->port[i].phy; - phy_cause = phy->ops->interrupt_handler(phy); - if (phy_cause & cphy_cause_link_change) - t1_link_changed(adapter, i); - } - break; - } - case CHBT_BOARD_CHT101: - if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */ - phy = adapter->port[0].phy; - phy_cause = phy->ops->interrupt_handler(phy); - if (phy_cause & cphy_cause_link_change) - t1_link_changed(adapter, 0); - } - break; - case CHBT_BOARD_7500: { - int p; - /* - * Elmer0's interrupt cause isn't useful here because there is - * only one bit that can be set for all 4 ports. This means - * we are forced to check every PHY's interrupt status - * register to see who initiated the interrupt. - */ - for_each_port(adapter, p) { - phy = adapter->port[p].phy; - phy_cause = phy->ops->interrupt_handler(phy); - if (phy_cause & cphy_cause_link_change) - t1_link_changed(adapter, p); - } - break; - } -#endif - case CHBT_BOARD_CHT210: - case CHBT_BOARD_N210: - case CHBT_BOARD_N110: - if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */ - phy = adapter->port[0].phy; - phy_cause = phy->ops->interrupt_handler(phy); - if (phy_cause & cphy_cause_link_change) - t1_link_changed(adapter, 0); - } - break; - case CHBT_BOARD_8000: - case CHBT_BOARD_CHT110: - if (netif_msg_intr(adapter)) - dev_dbg(&adapter->pdev->dev, - "External interrupt cause 0x%x\n", cause); - if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */ - struct cmac *mac = adapter->port[0].mac; - - mac->ops->interrupt_handler(mac); - } - if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */ - u32 mod_detect; - - t1_tpi_read(adapter, - A_ELMER0_GPI_STAT, &mod_detect); - if (netif_msg_link(adapter)) - dev_info(&adapter->pdev->dev, "XPAK %s\n", - mod_detect ? "removed" : "inserted"); - } - break; - } - t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause); - return 0; -} - -/* Enables all interrupts. */ -void t1_interrupts_enable(adapter_t *adapter) -{ - unsigned int i; - - adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP; - - t1_sge_intr_enable(adapter->sge); - t1_tp_intr_enable(adapter->tp); - if (adapter->espi) { - adapter->slow_intr_mask |= F_PL_INTR_ESPI; - t1_espi_intr_enable(adapter->espi); - } - - /* Enable MAC/PHY interrupts for each port. */ - for_each_port(adapter, i) { - adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac); - adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy); - } - - /* Enable PCIX & external chip interrupts on ASIC boards. */ - if (t1_is_asic(adapter)) { - u32 pl_intr = readl(adapter->regs + A_PL_ENABLE); - - /* PCI-X interrupts */ - pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, - 0xffffffff); - - adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX; - pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX; - writel(pl_intr, adapter->regs + A_PL_ENABLE); - } -} - -/* Disables all interrupts. */ -void t1_interrupts_disable(adapter_t* adapter) -{ - unsigned int i; - - t1_sge_intr_disable(adapter->sge); - t1_tp_intr_disable(adapter->tp); - if (adapter->espi) - t1_espi_intr_disable(adapter->espi); - - /* Disable MAC/PHY interrupts for each port. */ - for_each_port(adapter, i) { - adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac); - adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy); - } - - /* Disable PCIX & external chip interrupts. */ - if (t1_is_asic(adapter)) - writel(0, adapter->regs + A_PL_ENABLE); - - /* PCI-X interrupts */ - pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0); - - adapter->slow_intr_mask = 0; -} - -/* Clears all interrupts */ -void t1_interrupts_clear(adapter_t* adapter) -{ - unsigned int i; - - t1_sge_intr_clear(adapter->sge); - t1_tp_intr_clear(adapter->tp); - if (adapter->espi) - t1_espi_intr_clear(adapter->espi); - - /* Clear MAC/PHY interrupts for each port. */ - for_each_port(adapter, i) { - adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac); - adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy); - } - - /* Enable interrupts for external devices. */ - if (t1_is_asic(adapter)) { - u32 pl_intr = readl(adapter->regs + A_PL_CAUSE); - - writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX, - adapter->regs + A_PL_CAUSE); - } - - /* PCI-X interrupts */ - pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff); -} - -/* - * Slow path interrupt handler for ASICs. - */ -static int asic_slow_intr(adapter_t *adapter) -{ - u32 cause = readl(adapter->regs + A_PL_CAUSE); - - cause &= adapter->slow_intr_mask; - if (!cause) - return 0; - if (cause & F_PL_INTR_SGE_ERR) - t1_sge_intr_error_handler(adapter->sge); - if (cause & F_PL_INTR_TP) - t1_tp_intr_handler(adapter->tp); - if (cause & F_PL_INTR_ESPI) - t1_espi_intr_handler(adapter->espi); - if (cause & F_PL_INTR_PCIX) - t1_pci_intr_handler(adapter); - if (cause & F_PL_INTR_EXT) - t1_elmer0_ext_intr(adapter); - - /* Clear the interrupts just processed. */ - writel(cause, adapter->regs + A_PL_CAUSE); - readl(adapter->regs + A_PL_CAUSE); /* flush writes */ - return 1; -} - -int t1_slow_intr_handler(adapter_t *adapter) -{ -#ifdef CONFIG_CHELSIO_T1_1G - if (!t1_is_asic(adapter)) - return fpga_slow_intr(adapter); -#endif - return asic_slow_intr(adapter); -} - -/* Power sequencing is a work-around for Intel's XPAKs. */ -static void power_sequence_xpak(adapter_t* adapter) -{ - u32 mod_detect; - u32 gpo; - - /* Check for XPAK */ - t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect); - if (!(ELMER0_GP_BIT5 & mod_detect)) { - /* XPAK is present */ - t1_tpi_read(adapter, A_ELMER0_GPO, &gpo); - gpo |= ELMER0_GP_BIT18; - t1_tpi_write(adapter, A_ELMER0_GPO, gpo); - } -} - -int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi, - struct adapter_params *p) -{ - p->chip_version = bi->chip_term; - p->is_asic = (p->chip_version != CHBT_TERM_FPGA); - if (p->chip_version == CHBT_TERM_T1 || - p->chip_version == CHBT_TERM_T2 || - p->chip_version == CHBT_TERM_FPGA) { - u32 val = readl(adapter->regs + A_TP_PC_CONFIG); - - val = G_TP_PC_REV(val); - if (val == 2) - p->chip_revision = TERM_T1B; - else if (val == 3) - p->chip_revision = TERM_T2; - else - return -1; - } else - return -1; - return 0; -} - -/* - * Enable board components other than the Chelsio chip, such as external MAC - * and PHY. - */ -static int board_init(adapter_t *adapter, const struct board_info *bi) -{ - switch (bi->board) { - case CHBT_BOARD_8000: - case CHBT_BOARD_N110: - case CHBT_BOARD_N210: - case CHBT_BOARD_CHT210: - t1_tpi_par(adapter, 0xf); - t1_tpi_write(adapter, A_ELMER0_GPO, 0x800); - break; - case CHBT_BOARD_CHT110: - t1_tpi_par(adapter, 0xf); - t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800); - - /* TBD XXX Might not need. This fixes a problem - * described in the Intel SR XPAK errata. - */ - power_sequence_xpak(adapter); - break; -#ifdef CONFIG_CHELSIO_T1_1G - case CHBT_BOARD_CHT204E: - /* add config space write here */ - case CHBT_BOARD_CHT204: - case CHBT_BOARD_CHT204V: - case CHBT_BOARD_CHN204: - t1_tpi_par(adapter, 0xf); - t1_tpi_write(adapter, A_ELMER0_GPO, 0x804); - break; - case CHBT_BOARD_CHT101: - case CHBT_BOARD_7500: - t1_tpi_par(adapter, 0xf); - t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804); - break; -#endif - } - return 0; -} - -/* - * Initialize and configure the Terminator HW modules. Note that external - * MAC and PHYs are initialized separately. - */ -int t1_init_hw_modules(adapter_t *adapter) -{ - int err = -EIO; - const struct board_info *bi = board_info(adapter); - - if (!bi->clock_mc4) { - u32 val = readl(adapter->regs + A_MC4_CFG); - - writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG); - writel(F_M_BUS_ENABLE | F_TCAM_RESET, - adapter->regs + A_MC5_CONFIG); - } - - if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac, - bi->espi_nports)) - goto out_err; - - if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core)) - goto out_err; - - err = t1_sge_configure(adapter->sge, &adapter->params.sge); - if (err) - goto out_err; - - err = 0; -out_err: - return err; -} - -/* - * Determine a card's PCI mode. - */ -static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p) -{ - static const unsigned short speed_map[] = { 33, 66, 100, 133 }; - u32 pci_mode; - - pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode); - p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)]; - p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32; - p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0; -} - -/* - * Release the structures holding the SW per-Terminator-HW-module state. - */ -void t1_free_sw_modules(adapter_t *adapter) -{ - unsigned int i; - - for_each_port(adapter, i) { - struct cmac *mac = adapter->port[i].mac; - struct cphy *phy = adapter->port[i].phy; - - if (mac) - mac->ops->destroy(mac); - if (phy) - phy->ops->destroy(phy); - } - - if (adapter->sge) - t1_sge_destroy(adapter->sge); - if (adapter->tp) - t1_tp_destroy(adapter->tp); - if (adapter->espi) - t1_espi_destroy(adapter->espi); -} - -static void __devinit init_link_config(struct link_config *lc, - const struct board_info *bi) -{ - lc->supported = bi->caps; - lc->requested_speed = lc->speed = SPEED_INVALID; - lc->requested_duplex = lc->duplex = DUPLEX_INVALID; - lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; - if (lc->supported & SUPPORTED_Autoneg) { - lc->advertising = lc->supported; - lc->autoneg = AUTONEG_ENABLE; - lc->requested_fc |= PAUSE_AUTONEG; - } else { - lc->advertising = 0; - lc->autoneg = AUTONEG_DISABLE; - } -} - -/* - * Allocate and initialize the data structures that hold the SW state of - * the Terminator HW modules. - */ -int __devinit t1_init_sw_modules(adapter_t *adapter, - const struct board_info *bi) -{ - unsigned int i; - - adapter->params.brd_info = bi; - adapter->params.nports = bi->port_number; - adapter->params.stats_update_period = bi->gmac->stats_update_period; - - adapter->sge = t1_sge_create(adapter, &adapter->params.sge); - if (!adapter->sge) { - pr_err("%s: SGE initialization failed\n", - adapter->name); - goto error; - } - - if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) { - pr_err("%s: ESPI initialization failed\n", - adapter->name); - goto error; - } - - adapter->tp = t1_tp_create(adapter, &adapter->params.tp); - if (!adapter->tp) { - pr_err("%s: TP initialization failed\n", - adapter->name); - goto error; - } - - board_init(adapter, bi); - bi->mdio_ops->init(adapter, bi); - if (bi->gphy->reset) - bi->gphy->reset(adapter); - if (bi->gmac->reset) - bi->gmac->reset(adapter); - - for_each_port(adapter, i) { - u8 hw_addr[6]; - struct cmac *mac; - int phy_addr = bi->mdio_phybaseaddr + i; - - adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev, - phy_addr, bi->mdio_ops); - if (!adapter->port[i].phy) { - pr_err("%s: PHY %d initialization failed\n", - adapter->name, i); - goto error; - } - - adapter->port[i].mac = mac = bi->gmac->create(adapter, i); - if (!mac) { - pr_err("%s: MAC %d initialization failed\n", - adapter->name, i); - goto error; - } - - /* - * Get the port's MAC addresses either from the EEPROM if one - * exists or the one hardcoded in the MAC. - */ - if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY) - mac->ops->macaddress_get(mac, hw_addr); - else if (vpd_macaddress_get(adapter, i, hw_addr)) { - pr_err("%s: could not read MAC address from VPD ROM\n", - adapter->port[i].dev->name); - goto error; - } - memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN); - init_link_config(&adapter->port[i].link_config, bi); - } - - get_pci_mode(adapter, &adapter->params.pci); - t1_interrupts_clear(adapter); - return 0; - -error: - t1_free_sw_modules(adapter); - return -1; -} diff --git a/drivers/net/chelsio/suni1x10gexp_regs.h b/drivers/net/chelsio/suni1x10gexp_regs.h deleted file mode 100644 index d0f87d82566..00000000000 --- a/drivers/net/chelsio/suni1x10gexp_regs.h +++ /dev/null @@ -1,1643 +0,0 @@ -/***************************************************************************** - * * - * File: suni1x10gexp_regs.h * - * $Revision: 1.9 $ * - * $Date: 2005/06/22 00:17:04 $ * - * Description: * - * PMC/SIERRA (pm3393) MAC-PHY functionality. * - * part of the Chelsio 10Gb Ethernet Driver. * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License, version 2, as * - * published by the Free Software Foundation. * - * * - * You should have received a copy of the GNU General Public License along * - * with this program; if not, write to the Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - * * - * http://www.chelsio.com * - * * - * Maintainers: maintainers@chelsio.com * - * * - * Authors: PMC/SIERRA * - * * - * History: * - * * - ****************************************************************************/ - -#ifndef _CXGB_SUNI1x10GEXP_REGS_H_ -#define _CXGB_SUNI1x10GEXP_REGS_H_ - -/* -** Space allocated for each Exact Match Filter -** There are 8 filter configurations -*/ -#define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003 - -#define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER ) - -/* -** Space allocated for VLAN-Id Filter -** There are 8 filter configurations -*/ -#define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001 - -#define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER ) - -/* -** Space allocated for each MSTAT Counter -*/ -#define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004 - -#define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT ) - - -/******************************************************************************/ -/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/ -/******************************************************************************/ -/* Refer to the Register Bit Masks bellow for the naming of each register and */ -/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */ -/******************************************************************************/ - - -#define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000 -#define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001 -#define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002 -#define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003 -#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004 -#define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005 - -#define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006 -#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x0007 -#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x0008 -#define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x0009 -#define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A -#define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B - -#define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C -#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D -#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E -#define SUNI1x10GEXP_REG_FREE 0x000F - -#define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x0010 -#define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x0011 - -#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x0100 -#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x0101 -#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102 -#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x0103 -#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104 -#define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x0107 - -#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040 -#define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x2041 -#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042 -#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043 -#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045 -#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046 -#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047 -#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048 -#define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x2049 -#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) -#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) -#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) -#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)) -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068 -#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069 -#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A -#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B -#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C -#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D -#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E -#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F -#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070 - -#define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081 -#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084 -#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085 -#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086 -#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087 -#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088 -#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089 -#define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A -#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B -#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C -#define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092 - -#define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0 -#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1 -#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2 -#define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3 -#define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4 -#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5 -#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7 -#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8 -#define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9 -#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA -#define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB -#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC -#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD -#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE -#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF -#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0 -#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1 -#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2 -#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3 -#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4 -#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5 -#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6 -#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7 - -#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104 -#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105 -#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106 -#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107 -#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C -#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) -#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) -#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5 -#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6 -#define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM 51 - -#define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200 -#define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201 -#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209 -#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A -#define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D -#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E -#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F -#define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210 -#define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211 - -#define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240 -#define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241 -#define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242 -#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243 -#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244 -#define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245 - -#define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280 -#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282 -#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283 -#define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284 - -#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300 -#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301 -#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302 -#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303 -#define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304 -#define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305 - -#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040 -#define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041 -#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042 -#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043 -#define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044 -#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045 -#define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE 0x3046 -#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047 -#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048 -#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049 -#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER 0x304D -#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL 0x304E -#define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER 0x3051 -#define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG 0x3052 - -#define SUNI1x10GEXP_REG_XTEF_CTRL 0x3080 -#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084 -#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085 -#define SUNI1x10GEXP_REG_XTEF_VISIBILITY 0x3086 - -#define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG 0x30C0 -#define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG 0x30C1 -#define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG 0x30C2 -#define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES 0x30C3 -#define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES 0x30C4 -#define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES 0x30C5 -#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6 -#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7 -#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB 0x30C8 -#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB 0x30C9 -#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB 0x30CA -#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB 0x30CB -#define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK 0x30CC -#define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK 0x30CD -#define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK 0x30CE -#define SUNI1x10GEXP_REG_TXOAM_COSET 0x30CF -#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB 0x30D0 -#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB 0x30D1 -#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB 0x30D2 -#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB 0x30D3 - - -#define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG 0x3200 -#define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS 0x3201 -#define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS 0x3202 -#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT 0x3203 -#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT 0x3204 -#define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT 0x3205 -#define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT 0x3206 -#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD 0x3207 -#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C -#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D -#define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION 0x3210 - -#define SUNI1x10GEXP_REG_PL4IDU_CONFIG 0x3280 -#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282 -#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283 - - -/*----------------------------------------*/ -#define SUNI1x10GEXP_REG_MAX_OFFSET 0x3480 - -/******************************************************************************/ -/* -- End register offset definitions -- */ -/******************************************************************************/ - -/******************************************************************************/ -/** SUNI-1x10GE-XP REGISTER BIT MASKS **/ -/******************************************************************************/ - -#define SUNI1x10GEXP_BITMSK_BITS_1 0x00001 -#define SUNI1x10GEXP_BITMSK_BITS_2 0x00003 -#define SUNI1x10GEXP_BITMSK_BITS_3 0x00007 -#define SUNI1x10GEXP_BITMSK_BITS_4 0x0000f -#define SUNI1x10GEXP_BITMSK_BITS_5 0x0001f -#define SUNI1x10GEXP_BITMSK_BITS_6 0x0003f -#define SUNI1x10GEXP_BITMSK_BITS_7 0x0007f -#define SUNI1x10GEXP_BITMSK_BITS_8 0x000ff -#define SUNI1x10GEXP_BITMSK_BITS_9 0x001ff -#define SUNI1x10GEXP_BITMSK_BITS_10 0x003ff -#define SUNI1x10GEXP_BITMSK_BITS_11 0x007ff -#define SUNI1x10GEXP_BITMSK_BITS_12 0x00fff -#define SUNI1x10GEXP_BITMSK_BITS_13 0x01fff -#define SUNI1x10GEXP_BITMSK_BITS_14 0x03fff -#define SUNI1x10GEXP_BITMSK_BITS_15 0x07fff -#define SUNI1x10GEXP_BITMSK_BITS_16 0x0ffff - -#define mSUNI1x10GEXP_CLR_MSBITS_1(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_15) -#define mSUNI1x10GEXP_CLR_MSBITS_2(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_14) -#define mSUNI1x10GEXP_CLR_MSBITS_3(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_13) -#define mSUNI1x10GEXP_CLR_MSBITS_4(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_12) -#define mSUNI1x10GEXP_CLR_MSBITS_5(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_11) -#define mSUNI1x10GEXP_CLR_MSBITS_6(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_10) -#define mSUNI1x10GEXP_CLR_MSBITS_7(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_9) -#define mSUNI1x10GEXP_CLR_MSBITS_8(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_8) -#define mSUNI1x10GEXP_CLR_MSBITS_9(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_7) -#define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6) -#define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5) -#define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4) -#define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3) -#define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2) -#define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1) - -#define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0) - - - -/*---------------------------------------------------------------------------- - * Register 0x0001: S/UNI-1x10GE-XP Product Revision - * Bit 3-0 REVISION - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_REVISION 0x000F - -/*---------------------------------------------------------------------------- - * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control - * Bit 2 XAUI_ARESETB - * Bit 1 PL4_ARESETB - * Bit 0 DRESETB - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_XAUI_ARESET 0x0004 -#define SUNI1x10GEXP_BITMSK_PL4_ARESET 0x0002 -#define SUNI1x10GEXP_BITMSK_DRESETB 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control - * Bit 11 PL4IO_OUTCLKSEL - * Bit 9 SYSPCSLB - * Bit 8 LINEPCSLB - * Bit 7 MSTAT_BYPASS - * Bit 6 RXXG_BYPASS - * Bit 5 TXXG_BYPASS - * Bit 4 SOP_PAD_EN - * Bit 1 LOS_INV - * Bit 0 OVERRIDE_LOS - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL 0x0800 -#define SUNI1x10GEXP_BITMSK_SYSPCSLB 0x0200 -#define SUNI1x10GEXP_BITMSK_LINEPCSLB 0x0100 -#define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS 0x0080 -#define SUNI1x10GEXP_BITMSK_RXXG_BYPASS 0x0040 -#define SUNI1x10GEXP_BITMSK_TXXG_BYPASS 0x0020 -#define SUNI1x10GEXP_BITMSK_SOP_PAD_EN 0x0010 -#define SUNI1x10GEXP_BITMSK_LOS_INV 0x0002 -#define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0004: S/UNI-1x10GE-XP Device Status - * Bit 9 TOP_SXRA_EXPIRED - * Bit 8 TOP_MDIO_BUSY - * Bit 7 TOP_DTRB - * Bit 6 TOP_EXPIRED - * Bit 5 TOP_PAUSED - * Bit 4 TOP_PL4_ID_DOOL - * Bit 3 TOP_PL4_IS_DOOL - * Bit 2 TOP_PL4_ID_ROOL - * Bit 1 TOP_PL4_IS_ROOL - * Bit 0 TOP_PL4_OUT_ROOL - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200 -#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY 0x0100 -#define SUNI1x10GEXP_BITMSK_TOP_DTRB 0x0080 -#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040 -#define SUNI1x10GEXP_BITMSK_TOP_PAUSED 0x0020 -#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010 -#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008 -#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004 -#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL 0x0002 -#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0005: Global Performance Update and Clock Monitors - * Bit 15 TIP - * Bit 8 XAUI_REF_CLKA - * Bit 7 RXLANE3CLKA - * Bit 6 RXLANE2CLKA - * Bit 5 RXLANE1CLKA - * Bit 4 RXLANE0CLKA - * Bit 3 CSUCLKA - * Bit 2 TDCLKA - * Bit 1 RSCLKA - * Bit 0 RDCLKA - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TIP 0x8000 -#define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA 0x0100 -#define SUNI1x10GEXP_BITMSK_RXLANE3CLKA 0x0080 -#define SUNI1x10GEXP_BITMSK_RXLANE2CLKA 0x0040 -#define SUNI1x10GEXP_BITMSK_RXLANE1CLKA 0x0020 -#define SUNI1x10GEXP_BITMSK_RXLANE0CLKA 0x0010 -#define SUNI1x10GEXP_BITMSK_CSUCLKA 0x0008 -#define SUNI1x10GEXP_BITMSK_TDCLKA 0x0004 -#define SUNI1x10GEXP_BITMSK_RSCLKA 0x0002 -#define SUNI1x10GEXP_BITMSK_RDCLKA 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0006: MDIO Command - * Bit 4 MDIO_RDINC - * Bit 3 MDIO_RSTAT - * Bit 2 MDIO_LCTLD - * Bit 1 MDIO_LCTLA - * Bit 0 MDIO_SPRE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_MDIO_RDINC 0x0010 -#define SUNI1x10GEXP_BITMSK_MDIO_RSTAT 0x0008 -#define SUNI1x10GEXP_BITMSK_MDIO_LCTLD 0x0004 -#define SUNI1x10GEXP_BITMSK_MDIO_LCTLA 0x0002 -#define SUNI1x10GEXP_BITMSK_MDIO_SPRE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0007: MDIO Interrupt Enable - * Bit 0 MDIO_BUSY_EN - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0008: MDIO Interrupt Status - * Bit 0 MDIO_BUSYI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_MDIO_BUSYI 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0009: MMD PHY Address - * Bit 12-8 MDIO_DEVADR - * Bit 4-0 MDIO_PRTADR - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_MDIO_DEVADR 0x1F00 -#define SUNI1x10GEXP_BITOFF_MDIO_DEVADR 8 -#define SUNI1x10GEXP_BITMSK_MDIO_PRTADR 0x001F -#define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0 - -/*---------------------------------------------------------------------------- - * Register 0x000C: OAM Interface Control - * Bit 6 MDO_OD_ENB - * Bit 5 MDI_INV - * Bit 4 MDI_SEL - * Bit 3 RXOAMEN - * Bit 2 RXOAMCLKEN - * Bit 1 TXOAMEN - * Bit 0 TXOAMCLKEN - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_MDO_OD_ENB 0x0040 -#define SUNI1x10GEXP_BITMSK_MDI_INV 0x0020 -#define SUNI1x10GEXP_BITMSK_MDI_SEL 0x0010 -#define SUNI1x10GEXP_BITMSK_RXOAMEN 0x0008 -#define SUNI1x10GEXP_BITMSK_RXOAMCLKEN 0x0004 -#define SUNI1x10GEXP_BITMSK_TXOAMEN 0x0002 -#define SUNI1x10GEXP_BITMSK_TXOAMCLKEN 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status - * Bit 15 TOP_PL4IO_INT - * Bit 14 TOP_IRAM_INT - * Bit 13 TOP_ERAM_INT - * Bit 12 TOP_XAUI_INT - * Bit 11 TOP_MSTAT_INT - * Bit 10 TOP_RXXG_INT - * Bit 9 TOP_TXXG_INT - * Bit 8 TOP_XRF_INT - * Bit 7 TOP_XTEF_INT - * Bit 6 TOP_MDIO_BUSY_INT - * Bit 5 TOP_RXOAM_INT - * Bit 4 TOP_TXOAM_INT - * Bit 3 TOP_IFLX_INT - * Bit 2 TOP_EFLX_INT - * Bit 1 TOP_PL4ODP_INT - * Bit 0 TOP_PL4IDU_INT - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT 0x8000 -#define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT 0x4000 -#define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT 0x2000 -#define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT 0x1000 -#define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT 0x0800 -#define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT 0x0400 -#define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT 0x0200 -#define SUNI1x10GEXP_BITMSK_TOP_XRF_INT 0x0100 -#define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT 0x0080 -#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT 0x0040 -#define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT 0x0020 -#define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT 0x0010 -#define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT 0x0008 -#define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT 0x0004 -#define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT 0x0002 -#define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x000E:PM3393 Global interrupt enable - * Bit 15 TOP_INTE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000 - -/*---------------------------------------------------------------------------- - * Register 0x0010: XTEF Miscellaneous Control - * Bit 7 RF_VAL - * Bit 6 RF_OVERRIDE - * Bit 5 LF_VAL - * Bit 4 LF_OVERRIDE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RF_VAL 0x0080 -#define SUNI1x10GEXP_BITMSK_RF_OVERRIDE 0x0040 -#define SUNI1x10GEXP_BITMSK_LF_VAL 0x0020 -#define SUNI1x10GEXP_BITMSK_LF_OVERRIDE 0x0010 -#define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL 0x00F0 - -/*---------------------------------------------------------------------------- - * Register 0x0011: XRF Miscellaneous Control - * Bit 6-4 EN_IDLE_REP - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EN_IDLE_REP 0x0070 - -/*---------------------------------------------------------------------------- - * Register 0x0100: SERDES 3125 Configuration Register 1 - * Bit 10 RXEQB_3 - * Bit 8 RXEQB_2 - * Bit 6 RXEQB_1 - * Bit 4 RXEQB_0 - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXEQB 0x0FF0 -#define SUNI1x10GEXP_BITOFF_RXEQB_3 10 -#define SUNI1x10GEXP_BITOFF_RXEQB_2 8 -#define SUNI1x10GEXP_BITOFF_RXEQB_1 6 -#define SUNI1x10GEXP_BITOFF_RXEQB_0 4 - -/*---------------------------------------------------------------------------- - * Register 0x0101: SERDES 3125 Configuration Register 2 - * Bit 12 YSEL - * Bit 7 PRE_EMPH_3 - * Bit 6 PRE_EMPH_2 - * Bit 5 PRE_EMPH_1 - * Bit 4 PRE_EMPH_0 - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_YSEL 0x1000 -#define SUNI1x10GEXP_BITMSK_PRE_EMPH 0x00F0 -#define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 0x0080 -#define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 0x0040 -#define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 0x0020 -#define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 0x0010 - -/*---------------------------------------------------------------------------- - * Register 0x0102: SERDES 3125 Interrupt Enable Register - * Bit 3 LASIE - * Bit 2 SPLL_RAE - * Bit 1 MPLL_RAE - * Bit 0 PLL_LOCKE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_LASIE 0x0008 -#define SUNI1x10GEXP_BITMSK_SPLL_RAE 0x0004 -#define SUNI1x10GEXP_BITMSK_MPLL_RAE 0x0002 -#define SUNI1x10GEXP_BITMSK_PLL_LOCKE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0103: SERDES 3125 Interrupt Visibility Register - * Bit 3 LASIV - * Bit 2 SPLL_RAV - * Bit 1 MPLL_RAV - * Bit 0 PLL_LOCKV - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_LASIV 0x0008 -#define SUNI1x10GEXP_BITMSK_SPLL_RAV 0x0004 -#define SUNI1x10GEXP_BITMSK_MPLL_RAV 0x0002 -#define SUNI1x10GEXP_BITMSK_PLL_LOCKV 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0104: SERDES 3125 Interrupt Status Register - * Bit 3 LASII - * Bit 2 SPLL_RAI - * Bit 1 MPLL_RAI - * Bit 0 PLL_LOCKI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_LASII 0x0008 -#define SUNI1x10GEXP_BITMSK_SPLL_RAI 0x0004 -#define SUNI1x10GEXP_BITMSK_MPLL_RAI 0x0002 -#define SUNI1x10GEXP_BITMSK_PLL_LOCKI 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x0107: SERDES 3125 Test Configuration - * Bit 12 DUALTX - * Bit 10 HC_1 - * Bit 9 HC_0 - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_DUALTX 0x1000 -#define SUNI1x10GEXP_BITMSK_HC 0x0600 -#define SUNI1x10GEXP_BITOFF_HC_0 9 - -/*---------------------------------------------------------------------------- - * Register 0x2040: RXXG Configuration 1 - * Bit 15 RXXG_RXEN - * Bit 14 RXXG_ROCF - * Bit 13 RXXG_PAD_STRIP - * Bit 10 RXXG_PUREP - * Bit 9 RXXG_LONGP - * Bit 8 RXXG_PARF - * Bit 7 RXXG_FLCHK - * Bit 5 RXXG_PASS_CTRL - * Bit 3 RXXG_CRC_STRIP - * Bit 2-0 RXXG_MIFG - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000 -#define SUNI1x10GEXP_BITMSK_RXXG_ROCF 0x4000 -#define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP 0x2000 -#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400 -#define SUNI1x10GEXP_BITMSK_RXXG_LONGP 0x0200 -#define SUNI1x10GEXP_BITMSK_RXXG_PARF 0x0100 -#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080 -#define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL 0x0020 -#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008 - -/*---------------------------------------------------------------------------- - * Register 0x02041: RXXG Configuration 2 - * Bit 7-0 RXXG_HDRSIZE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE 0x00FF - -/*---------------------------------------------------------------------------- - * Register 0x2042: RXXG Configuration 3 - * Bit 15 RXXG_MIN_LERRE - * Bit 14 RXXG_MAX_LERRE - * Bit 12 RXXG_LINE_ERRE - * Bit 10 RXXG_RX_OVRE - * Bit 9 RXXG_ADR_FILTERE - * Bit 8 RXXG_ERR_FILTERE - * Bit 5 RXXG_PRMB_ERRE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE 0x8000 -#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE 0x4000 -#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE 0x1000 -#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE 0x0400 -#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE 0x0200 -#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE 0x0100 -#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020 - -/*---------------------------------------------------------------------------- - * Register 0x2043: RXXG Interrupt - * Bit 15 RXXG_MIN_LERRI - * Bit 14 RXXG_MAX_LERRI - * Bit 12 RXXG_LINE_ERRI - * Bit 10 RXXG_RX_OVRI - * Bit 9 RXXG_ADR_FILTERI - * Bit 8 RXXG_ERR_FILTERI - * Bit 5 RXXG_PRMB_ERRE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI 0x8000 -#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI 0x4000 -#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI 0x1000 -#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI 0x0400 -#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI 0x0200 -#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI 0x0100 -#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020 - -/*---------------------------------------------------------------------------- - * Register 0x2049: RXXG Receive FIFO Threshold - * Bit 2-0 RXXG_CUT_THRU - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU 0x0007 -#define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0 - -/*---------------------------------------------------------------------------- - * Register 0x2062H - 0x2069: RXXG Exact Match VID - * Bit 11-0 RXXG_VID_MATCH - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH 0x0FFF -#define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0 - -/*---------------------------------------------------------------------------- - * Register 0x206EH - 0x206F: RXXG Address Filter Control - * Bit 3 RXXG_FORWARD_ENABLE - * Bit 2 RXXG_VLAN_ENABLE - * Bit 1 RXXG_SRC_ADDR - * Bit 0 RXXG_MATCH_ENABLE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE 0x0008 -#define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE 0x0004 -#define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR 0x0002 -#define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x2070: RXXG Address Filter Control 2 - * Bit 1 RXXG_PMODE - * Bit 0 RXXG_MHASH_EN - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXXG_PMODE 0x0002 -#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x2081: XRF Control Register 2 - * Bit 6 EN_PKT_GEN - * Bit 4-2 PATT - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EN_PKT_GEN 0x0040 -#define SUNI1x10GEXP_BITMSK_PATT 0x001C -#define SUNI1x10GEXP_BITOFF_PATT 2 - -/*---------------------------------------------------------------------------- - * Register 0x2088: XRF Interrupt Enable - * Bit 12-9 LANE_HICERE - * Bit 8-5 HS_SD_LANEE - * Bit 4 ALIGN_STATUS_ERRE - * Bit 3-0 LANE_SYNC_STAT_ERRE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_LANE_HICERE 0x1E00 -#define SUNI1x10GEXP_BITOFF_LANE_HICERE 9 -#define SUNI1x10GEXP_BITMSK_HS_SD_LANEE 0x01E0 -#define SUNI1x10GEXP_BITOFF_HS_SD_LANEE 5 -#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE 0x0010 -#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE 0x000F -#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0 - -/*---------------------------------------------------------------------------- - * Register 0x2089: XRF Interrupt Status - * Bit 12-9 LANE_HICERI - * Bit 8-5 HS_SD_LANEI - * Bit 4 ALIGN_STATUS_ERRI - * Bit 3-0 LANE_SYNC_STAT_ERRI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_LANE_HICERI 0x1E00 -#define SUNI1x10GEXP_BITOFF_LANE_HICERI 9 -#define SUNI1x10GEXP_BITMSK_HS_SD_LANEI 0x01E0 -#define SUNI1x10GEXP_BITOFF_HS_SD_LANEI 5 -#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI 0x0010 -#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI 0x000F -#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0 - -/*---------------------------------------------------------------------------- - * Register 0x208A: XRF Error Status - * Bit 8-5 HS_SD_LANE - * Bit 4 ALIGN_STATUS_ERR - * Bit 3-0 LANE_SYNC_STAT_ERR - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 0x0100 -#define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 0x0080 -#define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 0x0040 -#define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 0x0020 -#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR 0x0010 -#define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR 0x0008 -#define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR 0x0004 -#define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR 0x0002 -#define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x208B: XRF Diagnostic Interrupt Enable - * Bit 7-4 LANE_OVERRUNE - * Bit 3-0 LANE_UNDERRUNE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE 0x00F0 -#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE 4 -#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE 0x000F -#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0 - -/*---------------------------------------------------------------------------- - * Register 0x208C: XRF Diagnostic Interrupt Status - * Bit 7-4 LANE_OVERRUNI - * Bit 3-0 LANE_UNDERRUNI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI 0x00F0 -#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI 4 -#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI 0x000F -#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0 - -/*---------------------------------------------------------------------------- - * Register 0x20C0: RXOAM Configuration - * Bit 15 RXOAM_BUSY - * Bit 14-12 RXOAM_F2_SEL - * Bit 10-8 RXOAM_F1_SEL - * Bit 7-6 RXOAM_FILTER_CTRL - * Bit 5-0 RXOAM_PX_EN - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXOAM_BUSY 0x8000 -#define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL 0x7000 -#define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL 12 -#define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL 0x0700 -#define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL 8 -#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL 0x00C0 -#define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL 6 -#define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN 0x003F -#define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 0 - -/*---------------------------------------------------------------------------- - * Register 0x20C1,0x20C2: RXOAM Filter Configuration - * Bit 15-8 RXOAM_FX_MASK - * Bit 7-0 RXOAM_FX_VAL - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK 0xFF00 -#define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK 8 -#define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL 0x00FF -#define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 0 - -/*---------------------------------------------------------------------------- - * Register 0x20C3: RXOAM Configuration Register 2 - * Bit 13 RXOAM_REC_BYTE_VAL - * Bit 11-10 RXOAM_BYPASS_MODE - * Bit 5-0 RXOAM_PX_CLEAR - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL 0x2000 -#define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE 0x0C00 -#define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE 10 -#define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR 0x003F -#define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 0 - -/*---------------------------------------------------------------------------- - * Register 0x20C4: RXOAM HEC Configuration - * Bit 15-8 RXOAM_COSET - * Bit 2 RXOAM_HEC_ERR_PKT - * Bit 0 RXOAM_HEC_EN - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXOAM_COSET 0xFF00 -#define SUNI1x10GEXP_BITOFF_RXOAM_COSET 8 -#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT 0x0004 -#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x20C7: RXOAM Interrupt Enable - * Bit 10 RXOAM_FILTER_THRSHE - * Bit 9 RXOAM_OAM_ERRE - * Bit 8 RXOAM_HECE_THRSHE - * Bit 7 RXOAM_SOPE - * Bit 6 RXOAM_RFE - * Bit 5 RXOAM_LFE - * Bit 4 RXOAM_DV_ERRE - * Bit 3 RXOAM_DATA_INVALIDE - * Bit 2 RXOAM_FILTER_DROPE - * Bit 1 RXOAM_HECE - * Bit 0 RXOAM_OFLE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE 0x0400 -#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE 0x0200 -#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE 0x0100 -#define SUNI1x10GEXP_BITMSK_RXOAM_SOPE 0x0080 -#define SUNI1x10GEXP_BITMSK_RXOAM_RFE 0x0040 -#define SUNI1x10GEXP_BITMSK_RXOAM_LFE 0x0020 -#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE 0x0010 -#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE 0x0008 -#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE 0x0004 -#define SUNI1x10GEXP_BITMSK_RXOAM_HECE 0x0002 -#define SUNI1x10GEXP_BITMSK_RXOAM_OFLE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x20C8: RXOAM Interrupt Status - * Bit 10 RXOAM_FILTER_THRSHI - * Bit 9 RXOAM_OAM_ERRI - * Bit 8 RXOAM_HECE_THRSHI - * Bit 7 RXOAM_SOPI - * Bit 6 RXOAM_RFI - * Bit 5 RXOAM_LFI - * Bit 4 RXOAM_DV_ERRI - * Bit 3 RXOAM_DATA_INVALIDI - * Bit 2 RXOAM_FILTER_DROPI - * Bit 1 RXOAM_HECI - * Bit 0 RXOAM_OFLI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI 0x0400 -#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI 0x0200 -#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI 0x0100 -#define SUNI1x10GEXP_BITMSK_RXOAM_SOPI 0x0080 -#define SUNI1x10GEXP_BITMSK_RXOAM_RFI 0x0040 -#define SUNI1x10GEXP_BITMSK_RXOAM_LFI 0x0020 -#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI 0x0010 -#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI 0x0008 -#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI 0x0004 -#define SUNI1x10GEXP_BITMSK_RXOAM_HECI 0x0002 -#define SUNI1x10GEXP_BITMSK_RXOAM_OFLI 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x20C9: RXOAM Status - * Bit 10 RXOAM_FILTER_THRSHV - * Bit 8 RXOAM_HECE_THRSHV - * Bit 6 RXOAM_RFV - * Bit 5 RXOAM_LFV - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV 0x0400 -#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV 0x0100 -#define SUNI1x10GEXP_BITMSK_RXOAM_RFV 0x0040 -#define SUNI1x10GEXP_BITMSK_RXOAM_LFV 0x0020 - -/*---------------------------------------------------------------------------- - * Register 0x2100: MSTAT Control - * Bit 2 MSTAT_WRITE - * Bit 1 MSTAT_CLEAR - * Bit 0 MSTAT_SNAP - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE 0x0004 -#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002 -#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x2109: MSTAT Counter Write Address - * Bit 5-0 MSTAT_WRITE_ADDRESS - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F -#define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0 - -/*---------------------------------------------------------------------------- - * Register 0x2200: IFLX Global Configuration Register - * Bit 15 IFLX_IRCU_ENABLE - * Bit 14 IFLX_IDSWT_ENABLE - * Bit 13-0 IFLX_IFD_CNT - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE 0x8000 -#define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE 0x4000 -#define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT 0x3FFF -#define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 0 - -/*---------------------------------------------------------------------------- - * Register 0x2209: IFLX FIFO Overflow Enable - * Bit 0 IFLX_OVFE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x220A: IFLX FIFO Overflow Interrupt - * Bit 0 IFLX_OVFI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x220D: IFLX Indirect Channel Address - * Bit 15 IFLX_BUSY - * Bit 14 IFLX_RWB - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_IFLX_BUSY 0x8000 -#define SUNI1x10GEXP_BITMSK_IFLX_RWB 0x4000 - -/*---------------------------------------------------------------------------- - * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision - * Bit 9-0 IFLX_LOLIM - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_IFLX_LOLIM 0x03FF -#define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 0 - -/*---------------------------------------------------------------------------- - * Register 0x220F: IFLX Indirect Logical FIFO High Limit - * Bit 9-0 IFLX_HILIM - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_IFLX_HILIM 0x03FF -#define SUNI1x10GEXP_BITOFF_IFLX_HILIM 0 - -/*---------------------------------------------------------------------------- - * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit - * Bit 15 IFLX_FULL - * Bit 14 IFLX_AFULL - * Bit 13-0 IFLX_AFTH - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_IFLX_FULL 0x8000 -#define SUNI1x10GEXP_BITMSK_IFLX_AFULL 0x4000 -#define SUNI1x10GEXP_BITMSK_IFLX_AFTH 0x3FFF -#define SUNI1x10GEXP_BITOFF_IFLX_AFTH 0 - -/*---------------------------------------------------------------------------- - * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit - * Bit 15 IFLX_EMPTY - * Bit 14 IFLX_AEMPTY - * Bit 13-0 IFLX_AETH - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_IFLX_EMPTY 0x8000 -#define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY 0x4000 -#define SUNI1x10GEXP_BITMSK_IFLX_AETH 0x3FFF -#define SUNI1x10GEXP_BITOFF_IFLX_AETH 0 - -/*---------------------------------------------------------------------------- - * Register 0x2240: PL4MOS Configuration Register - * Bit 3 PL4MOS_RE_INIT - * Bit 2 PL4MOS_EN - * Bit 1 PL4MOS_NO_STATUS - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT 0x0008 -#define SUNI1x10GEXP_BITMSK_PL4MOS_EN 0x0004 -#define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS 0x0002 - -/*---------------------------------------------------------------------------- - * Register 0x2243: PL4MOS MaxBurst1 Register - * Bit 11-0 PL4MOS_MAX_BURST1 - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 0x0FFF -#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 0 - -/*---------------------------------------------------------------------------- - * Register 0x2244: PL4MOS MaxBurst2 Register - * Bit 11-0 PL4MOS_MAX_BURST2 - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 0x0FFF -#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 0 - -/*---------------------------------------------------------------------------- - * Register 0x2245: PL4MOS Transfer Size Register - * Bit 7-0 PL4MOS_MAX_TRANSFER - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER 0x00FF -#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 0 - -/*---------------------------------------------------------------------------- - * Register 0x2280: PL4ODP Configuration - * Bit 15-12 PL4ODP_REPEAT_T - * Bit 8 PL4ODP_SOP_RULE - * Bit 1 PL4ODP_EN_PORTS - * Bit 0 PL4ODP_EN_DFWD - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T 0xF000 -#define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T 12 -#define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE 0x0100 -#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS 0x0002 -#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x2282: PL4ODP Interrupt Mask - * Bit 0 PL4ODP_OUT_DISE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE 0x0001 - - - -#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE 0x0080 -#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE 0x0040 -#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE 0x0008 -#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE 0x0004 -#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE 0x0002 - - -/*---------------------------------------------------------------------------- - * Register 0x2283: PL4ODP Interrupt - * Bit 0 PL4ODP_OUT_DISI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI 0x0001 - - - -#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI 0x0080 -#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI 0x0040 -#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI 0x0008 -#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI 0x0004 -#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI 0x0002 - -/*---------------------------------------------------------------------------- - * Register 0x2300: PL4IO Lock Detect Status - * Bit 15 PL4IO_OUT_ROOLV - * Bit 12 PL4IO_IS_ROOLV - * Bit 11 PL4IO_DIP2_ERRV - * Bit 8 PL4IO_ID_ROOLV - * Bit 4 PL4IO_IS_DOOLV - * Bit 0 PL4IO_ID_DOOLV - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV 0x8000 -#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV 0x1000 -#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV 0x0800 -#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV 0x0100 -#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV 0x0010 -#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x2301: PL4IO Lock Detect Change - * Bit 15 PL4IO_OUT_ROOLI - * Bit 12 PL4IO_IS_ROOLI - * Bit 11 PL4IO_DIP2_ERRI - * Bit 8 PL4IO_ID_ROOLI - * Bit 4 PL4IO_IS_DOOLI - * Bit 0 PL4IO_ID_DOOLI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI 0x8000 -#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI 0x1000 -#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI 0x0800 -#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI 0x0100 -#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI 0x0010 -#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x2302: PL4IO Lock Detect Mask - * Bit 15 PL4IO_OUT_ROOLE - * Bit 12 PL4IO_IS_ROOLE - * Bit 11 PL4IO_DIP2_ERRE - * Bit 8 PL4IO_ID_ROOLE - * Bit 4 PL4IO_IS_DOOLE - * Bit 0 PL4IO_ID_DOOLE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE 0x8000 -#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE 0x1000 -#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE 0x0800 -#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE 0x0100 -#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE 0x0010 -#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x2303: PL4IO Lock Detect Limits - * Bit 15-8 PL4IO_REF_LIMIT - * Bit 7-0 PL4IO_TRAN_LIMIT - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT 0xFF00 -#define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT 8 -#define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT 0x00FF -#define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 0 - -/*---------------------------------------------------------------------------- - * Register 0x2304: PL4IO Calendar Repetitions - * Bit 15-8 PL4IO_IN_MUL - * Bit 7-0 PL4IO_OUT_MUL - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL 0xFF00 -#define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL 8 -#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL 0x00FF -#define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 0 - -/*---------------------------------------------------------------------------- - * Register 0x2305: PL4IO Configuration - * Bit 15 PL4IO_DIP2_ERR_CHK - * Bit 11 PL4IO_ODAT_DIS - * Bit 10 PL4IO_TRAIN_DIS - * Bit 9 PL4IO_OSTAT_DIS - * Bit 8 PL4IO_ISTAT_DIS - * Bit 7 PL4IO_NO_ISTAT - * Bit 6 PL4IO_STAT_OUTSEL - * Bit 5 PL4IO_INSEL - * Bit 4 PL4IO_DLSEL - * Bit 1-0 PL4IO_OUTSEL - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK 0x8000 -#define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS 0x0800 -#define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS 0x0400 -#define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS 0x0200 -#define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS 0x0100 -#define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT 0x0080 -#define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL 0x0040 -#define SUNI1x10GEXP_BITMSK_PL4IO_INSEL 0x0020 -#define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL 0x0010 -#define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL 0x0003 -#define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 0 - -/*---------------------------------------------------------------------------- - * Register 0x3040: TXXG Configuration Register 1 - * Bit 15 TXXG_TXEN0 - * Bit 13 TXXG_HOSTPAUSE - * Bit 12-7 TXXG_IPGT - * Bit 5 TXXG_32BIT_ALIGN - * Bit 4 TXXG_CRCEN - * Bit 3 TXXG_FCTX - * Bit 2 TXXG_FCRX - * Bit 1 TXXG_PADEN - * Bit 0 TXXG_SPRE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000 -#define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE 0x2000 -#define SUNI1x10GEXP_BITMSK_TXXG_IPGT 0x1F80 -#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7 -#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020 -#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010 -#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008 -#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004 -#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002 -#define SUNI1x10GEXP_BITMSK_TXXG_SPRE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x3041: TXXG Configuration Register 2 - * Bit 7-0 TXXG_HDRSIZE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE 0x00FF - -/*---------------------------------------------------------------------------- - * Register 0x3042: TXXG Configuration Register 3 - * Bit 15 TXXG_FIFO_ERRE - * Bit 14 TXXG_FIFO_UDRE - * Bit 13 TXXG_MAX_LERRE - * Bit 12 TXXG_MIN_LERRE - * Bit 11 TXXG_XFERE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE 0x8000 -#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE 0x4000 -#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE 0x2000 -#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE 0x1000 -#define SUNI1x10GEXP_BITMSK_TXXG_XFERE 0x0800 - -/*---------------------------------------------------------------------------- - * Register 0x3043: TXXG Interrupt - * Bit 15 TXXG_FIFO_ERRI - * Bit 14 TXXG_FIFO_UDRI - * Bit 13 TXXG_MAX_LERRI - * Bit 12 TXXG_MIN_LERRI - * Bit 11 TXXG_XFERI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI 0x8000 -#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI 0x4000 -#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI 0x2000 -#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI 0x1000 -#define SUNI1x10GEXP_BITMSK_TXXG_XFERI 0x0800 - -/*---------------------------------------------------------------------------- - * Register 0x3044: TXXG Status Register - * Bit 1 TXXG_TXACTIVE - * Bit 0 TXXG_PAUSED - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE 0x0002 -#define SUNI1x10GEXP_BITMSK_TXXG_PAUSED 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register - * Bit 7-0 TXXG_TX_MINFR - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR 0x00FF -#define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 0 - -/*---------------------------------------------------------------------------- - * Register 0x3052: TXXG Pause Quantum Value Configuration Register - * Bit 7-0 TXXG_FC_PAUSE_QNTM - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM 0x00FF -#define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 0 - -/*---------------------------------------------------------------------------- - * Register 0x3080: XTEF Control - * Bit 3-0 XTEF_FORCE_PARITY_ERR - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR 0x000F -#define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR 0 - -/*---------------------------------------------------------------------------- - * Register 0x3084: XTEF Interrupt Event Register - * Bit 0 XTEF_LOST_SYNCI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x3085: XTEF Interrupt Enable Register - * Bit 0 XTEF_LOST_SYNCE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x3086: XTEF Visibility Register - * Bit 0 XTEF_LOST_SYNCV - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x30C0: TXOAM OAM Configuration - * Bit 15 TXOAM_HEC_EN - * Bit 14 TXOAM_EMPTYCODE_EN - * Bit 13 TXOAM_FORCE_IDLE - * Bit 12 TXOAM_IGNORE_IDLE - * Bit 11-6 TXOAM_PX_OVERWRITE - * Bit 5-0 TXOAM_PX_SEL - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN 0x8000 -#define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN 0x4000 -#define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE 0x2000 -#define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE 0x1000 -#define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE 0x0FC0 -#define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE 6 -#define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL 0x003F -#define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 0 - -/*---------------------------------------------------------------------------- - * Register 0x30C1: TXOAM Mini-Packet Rate Configuration - * Bit 15 TXOAM_MINIDIS - * Bit 14 TXOAM_BUSY - * Bit 13 TXOAM_TRANS_EN - * Bit 10-0 TXOAM_MINIRATE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS 0x8000 -#define SUNI1x10GEXP_BITMSK_TXOAM_BUSY 0x4000 -#define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN 0x2000 -#define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE 0x07FF - -/*---------------------------------------------------------------------------- - * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration - * Bit 13-10 TXOAM_FTHRESH - * Bit 9-6 TXOAM_MINIPOST - * Bit 5-0 TXOAM_MINIPRE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH 0x3C00 -#define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH 10 -#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST 0x03C0 -#define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST 6 -#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE 0x003F - -/*---------------------------------------------------------------------------- - * Register 0x30C6: TXOAM Interrupt Enable - * Bit 2 TXOAM_SOP_ERRE - * Bit 1 TXOAM_OFLE - * Bit 0 TXOAM_ERRE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE 0x0004 -#define SUNI1x10GEXP_BITMSK_TXOAM_OFLE 0x0002 -#define SUNI1x10GEXP_BITMSK_TXOAM_ERRE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x30C7: TXOAM Interrupt Status - * Bit 2 TXOAM_SOP_ERRI - * Bit 1 TXOAM_OFLI - * Bit 0 TXOAM_ERRI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI 0x0004 -#define SUNI1x10GEXP_BITMSK_TXOAM_OFLI 0x0002 -#define SUNI1x10GEXP_BITMSK_TXOAM_ERRI 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x30CF: TXOAM Coset - * Bit 7-0 TXOAM_COSET - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_TXOAM_COSET 0x00FF - -/*---------------------------------------------------------------------------- - * Register 0x3200: EFLX Global Configuration - * Bit 15 EFLX_ERCU_EN - * Bit 7 EFLX_EN_EDSWT - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN 0x8000 -#define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT 0x0080 - -/*---------------------------------------------------------------------------- - * Register 0x3201: EFLX ERCU Global Status - * Bit 13 EFLX_OVF_ERR - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR 0x2000 - -/*---------------------------------------------------------------------------- - * Register 0x3202: EFLX Indirect Channel Address - * Bit 15 EFLX_BUSY - * Bit 14 EFLX_RDWRB - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_BUSY 0x8000 -#define SUNI1x10GEXP_BITMSK_EFLX_RDWRB 0x4000 - -/*---------------------------------------------------------------------------- - * Register 0x3203: EFLX Indirect Logical FIFO Low Limit - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_LOLIM 0x03FF -#define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 0 - -/*---------------------------------------------------------------------------- - * Register 0x3204: EFLX Indirect Logical FIFO High Limit - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_HILIM 0x03FF -#define SUNI1x10GEXP_BITOFF_EFLX_HILIM 0 - -/*---------------------------------------------------------------------------- - * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit - * Bit 15 EFLX_FULL - * Bit 14 EFLX_AFULL - * Bit 13-0 EFLX_AFTH - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_FULL 0x8000 -#define SUNI1x10GEXP_BITMSK_EFLX_AFULL 0x4000 -#define SUNI1x10GEXP_BITMSK_EFLX_AFTH 0x3FFF -#define SUNI1x10GEXP_BITOFF_EFLX_AFTH 0 - -/*---------------------------------------------------------------------------- - * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit - * Bit 15 EFLX_EMPTY - * Bit 14 EFLX_AEMPTY - * Bit 13-0 EFLX_AETH - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_EMPTY 0x8000 -#define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY 0x4000 -#define SUNI1x10GEXP_BITMSK_EFLX_AETH 0x3FFF -#define SUNI1x10GEXP_BITOFF_EFLX_AETH 0 - -/*---------------------------------------------------------------------------- - * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU 0x3FFF -#define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 0 - -/*---------------------------------------------------------------------------- - * Register 0x320C: EFLX FIFO Overflow Error Enable - * Bit 0 EFLX_OVFE - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_OVFE 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x320D: EFLX FIFO Overflow Error Indication - * Bit 0 EFLX_OVFI - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_OVFI 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x3210: EFLX Channel Provision - * Bit 0 EFLX_PROV - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_EFLX_PROV 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x3280: PL4IDU Configuration - * Bit 2 PL4IDU_SYNCH_ON_TRAIN - * Bit 1 PL4IDU_EN_PORTS - * Bit 0 PL4IDU_EN_DFWD - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN 0x0004 -#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS 0x0002 -#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD 0x0001 - -/*---------------------------------------------------------------------------- - * Register 0x3282: PL4IDU Interrupt Mask - * Bit 1 PL4IDU_DIP4E - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E 0x0002 - -/*---------------------------------------------------------------------------- - * Register 0x3283: PL4IDU Interrupt - * Bit 1 PL4IDU_DIP4I - *----------------------------------------------------------------------------*/ -#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I 0x0002 - -#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */ - diff --git a/drivers/net/chelsio/tp.c b/drivers/net/chelsio/tp.c deleted file mode 100644 index 8bed4a59e65..00000000000 --- a/drivers/net/chelsio/tp.c +++ /dev/null @@ -1,171 +0,0 @@ -/* $Date: 2006/02/07 04:21:54 $ $RCSfile: tp.c,v $ $Revision: 1.73 $ */ -#include "common.h" -#include "regs.h" -#include "tp.h" -#ifdef CONFIG_CHELSIO_T1_1G -#include "fpga_defs.h" -#endif - -struct petp { - adapter_t *adapter; -}; - -/* Pause deadlock avoidance parameters */ -#define DROP_MSEC 16 -#define DROP_PKTS_CNT 1 - -static void tp_init(adapter_t * ap, const struct tp_params *p, - unsigned int tp_clk) -{ - u32 val; - - if (!t1_is_asic(ap)) - return; - - val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM | - F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET; - if (!p->pm_size) - val |= F_OFFLOAD_DISABLE; - else - val |= F_TP_IN_ESPI_CHECK_IP_CSUM | F_TP_IN_ESPI_CHECK_TCP_CSUM; - writel(val, ap->regs + A_TP_IN_CONFIG); - writel(F_TP_OUT_CSPI_CPL | - F_TP_OUT_ESPI_ETHERNET | - F_TP_OUT_ESPI_GENERATE_IP_CSUM | - F_TP_OUT_ESPI_GENERATE_TCP_CSUM, ap->regs + A_TP_OUT_CONFIG); - writel(V_IP_TTL(64) | - F_PATH_MTU /* IP DF bit */ | - V_5TUPLE_LOOKUP(p->use_5tuple_mode) | - V_SYN_COOKIE_PARAMETER(29), ap->regs + A_TP_GLOBAL_CONFIG); - /* - * Enable pause frame deadlock prevention. - */ - if (is_T2(ap) && ap->params.nports > 1) { - u32 drop_ticks = DROP_MSEC * (tp_clk / 1000); - - writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | - V_DROP_TICKS_CNT(drop_ticks) | - V_NUM_PKTS_DROPPED(DROP_PKTS_CNT), - ap->regs + A_TP_TX_DROP_CONFIG); - } -} - -void t1_tp_destroy(struct petp *tp) -{ - kfree(tp); -} - -struct petp *__devinit t1_tp_create(adapter_t * adapter, struct tp_params *p) -{ - struct petp *tp = kzalloc(sizeof(*tp), GFP_KERNEL); - - if (!tp) - return NULL; - - tp->adapter = adapter; - - return tp; -} - -void t1_tp_intr_enable(struct petp *tp) -{ - u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE); - -#ifdef CONFIG_CHELSIO_T1_1G - if (!t1_is_asic(tp->adapter)) { - /* FPGA */ - writel(0xffffffff, - tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); - writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, - tp->adapter->regs + A_PL_ENABLE); - } else -#endif - { - /* We don't use any TP interrupts */ - writel(0, tp->adapter->regs + A_TP_INT_ENABLE); - writel(tp_intr | F_PL_INTR_TP, - tp->adapter->regs + A_PL_ENABLE); - } -} - -void t1_tp_intr_disable(struct petp *tp) -{ - u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE); - -#ifdef CONFIG_CHELSIO_T1_1G - if (!t1_is_asic(tp->adapter)) { - /* FPGA */ - writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); - writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, - tp->adapter->regs + A_PL_ENABLE); - } else -#endif - { - writel(0, tp->adapter->regs + A_TP_INT_ENABLE); - writel(tp_intr & ~F_PL_INTR_TP, - tp->adapter->regs + A_PL_ENABLE); - } -} - -void t1_tp_intr_clear(struct petp *tp) -{ -#ifdef CONFIG_CHELSIO_T1_1G - if (!t1_is_asic(tp->adapter)) { - writel(0xffffffff, - tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); - writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE); - return; - } -#endif - writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE); - writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE); -} - -int t1_tp_intr_handler(struct petp *tp) -{ - u32 cause; - -#ifdef CONFIG_CHELSIO_T1_1G - /* FPGA doesn't support TP interrupts. */ - if (!t1_is_asic(tp->adapter)) - return 1; -#endif - - cause = readl(tp->adapter->regs + A_TP_INT_CAUSE); - writel(cause, tp->adapter->regs + A_TP_INT_CAUSE); - return 0; -} - -static void set_csum_offload(struct petp *tp, u32 csum_bit, int enable) -{ - u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG); - - if (enable) - val |= csum_bit; - else - val &= ~csum_bit; - writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG); -} - -void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable) -{ - set_csum_offload(tp, F_IP_CSUM, enable); -} - -void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable) -{ - set_csum_offload(tp, F_TCP_CSUM, enable); -} - -/* - * Initialize TP state. tp_params contains initial settings for some TP - * parameters, particularly the one-time PM and CM settings. - */ -int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk) -{ - adapter_t *adapter = tp->adapter; - - tp_init(adapter, p, tp_clk); - writel(F_TP_RESET, adapter->regs + A_TP_RESET); - return 0; -} diff --git a/drivers/net/chelsio/tp.h b/drivers/net/chelsio/tp.h deleted file mode 100644 index dfd8ce25106..00000000000 --- a/drivers/net/chelsio/tp.h +++ /dev/null @@ -1,72 +0,0 @@ -/* $Date: 2005/03/07 23:59:05 $ $RCSfile: tp.h,v $ $Revision: 1.20 $ */ -#ifndef CHELSIO_TP_H -#define CHELSIO_TP_H - -#include "common.h" - -#define TP_MAX_RX_COALESCING_SIZE 16224U - -struct tp_mib_statistics { - - /* IP */ - u32 ipInReceive_hi; - u32 ipInReceive_lo; - u32 ipInHdrErrors_hi; - u32 ipInHdrErrors_lo; - u32 ipInAddrErrors_hi; - u32 ipInAddrErrors_lo; - u32 ipInUnknownProtos_hi; - u32 ipInUnknownProtos_lo; - u32 ipInDiscards_hi; - u32 ipInDiscards_lo; - u32 ipInDelivers_hi; - u32 ipInDelivers_lo; - u32 ipOutRequests_hi; - u32 ipOutRequests_lo; - u32 ipOutDiscards_hi; - u32 ipOutDiscards_lo; - u32 ipOutNoRoutes_hi; - u32 ipOutNoRoutes_lo; - u32 ipReasmTimeout; - u32 ipReasmReqds; - u32 ipReasmOKs; - u32 ipReasmFails; - - u32 reserved[8]; - - /* TCP */ - u32 tcpActiveOpens; - u32 tcpPassiveOpens; - u32 tcpAttemptFails; - u32 tcpEstabResets; - u32 tcpOutRsts; - u32 tcpCurrEstab; - u32 tcpInSegs_hi; - u32 tcpInSegs_lo; - u32 tcpOutSegs_hi; - u32 tcpOutSegs_lo; - u32 tcpRetransSeg_hi; - u32 tcpRetransSeg_lo; - u32 tcpInErrs_hi; - u32 tcpInErrs_lo; - u32 tcpRtoMin; - u32 tcpRtoMax; -}; - -struct petp; -struct tp_params; - -struct petp *t1_tp_create(adapter_t *adapter, struct tp_params *p); -void t1_tp_destroy(struct petp *tp); - -void t1_tp_intr_disable(struct petp *tp); -void t1_tp_intr_enable(struct petp *tp); -void t1_tp_intr_clear(struct petp *tp); -int t1_tp_intr_handler(struct petp *tp); - -void t1_tp_get_mib_statistics(adapter_t *adap, struct tp_mib_statistics *tps); -void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable); -void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable); -int t1_tp_set_coalescing_size(struct petp *tp, unsigned int size); -int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk); -#endif diff --git a/drivers/net/chelsio/vsc7326.c b/drivers/net/chelsio/vsc7326.c deleted file mode 100644 index b0cb388f5e1..00000000000 --- a/drivers/net/chelsio/vsc7326.c +++ /dev/null @@ -1,730 +0,0 @@ -/* $Date: 2006/04/28 19:20:06 $ $RCSfile: vsc7326.c,v $ $Revision: 1.19 $ */ - -/* Driver for Vitesse VSC7326 (Schaumburg) MAC */ - -#include "gmac.h" -#include "elmer0.h" -#include "vsc7326_reg.h" - -/* Update fast changing statistics every 15 seconds */ -#define STATS_TICK_SECS 15 -/* 30 minutes for full statistics update */ -#define MAJOR_UPDATE_TICKS (1800 / STATS_TICK_SECS) - -#define MAX_MTU 9600 - -/* The egress WM value 0x01a01fff should be used only when the - * interface is down (MAC port disabled). This is a workaround - * for disabling the T2/MAC flow-control. When the interface is - * enabled, the WM value should be set to 0x014a03F0. - */ -#define WM_DISABLE 0x01a01fff -#define WM_ENABLE 0x014a03F0 - -struct init_table { - u32 addr; - u32 data; -}; - -struct _cmac_instance { - u32 index; - u32 ticks; -}; - -#define INITBLOCK_SLEEP 0xffffffff - -static void vsc_read(adapter_t *adapter, u32 addr, u32 *val) -{ - u32 status, vlo, vhi; - int i; - - spin_lock_bh(&adapter->mac_lock); - t1_tpi_read(adapter, (addr << 2) + 4, &vlo); - i = 0; - do { - t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo); - t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi); - status = (vhi << 16) | vlo; - i++; - } while (((status & 1) == 0) && (i < 50)); - if (i == 50) - pr_err("Invalid tpi read from MAC, breaking loop.\n"); - - t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo); - t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi); - - *val = (vhi << 16) | vlo; - - /* pr_err("rd: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n", - ((addr&0xe000)>>13), ((addr&0x1e00)>>9), - ((addr&0x01fe)>>1), *val); */ - spin_unlock_bh(&adapter->mac_lock); -} - -static void vsc_write(adapter_t *adapter, u32 addr, u32 data) -{ - spin_lock_bh(&adapter->mac_lock); - t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF); - t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF); - /* pr_err("wr: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n", - ((addr&0xe000)>>13), ((addr&0x1e00)>>9), - ((addr&0x01fe)>>1), data); */ - spin_unlock_bh(&adapter->mac_lock); -} - -/* Hard reset the MAC. This wipes out *all* configuration. */ -static void vsc7326_full_reset(adapter_t* adapter) -{ - u32 val; - u32 result = 0xffff; - - t1_tpi_read(adapter, A_ELMER0_GPO, &val); - val &= ~1; - t1_tpi_write(adapter, A_ELMER0_GPO, val); - udelay(2); - val |= 0x1; /* Enable mac MAC itself */ - val |= 0x800; /* Turn off the red LED */ - t1_tpi_write(adapter, A_ELMER0_GPO, val); - mdelay(1); - vsc_write(adapter, REG_SW_RESET, 0x80000001); - do { - mdelay(1); - vsc_read(adapter, REG_SW_RESET, &result); - } while (result != 0x0); -} - -static struct init_table vsc7326_reset[] = { - { REG_IFACE_MODE, 0x00000000 }, - { REG_CRC_CFG, 0x00000020 }, - { REG_PLL_CLK_SPEED, 0x00050c00 }, - { REG_PLL_CLK_SPEED, 0x00050c00 }, - { REG_MSCH, 0x00002f14 }, - { REG_SPI4_MISC, 0x00040409 }, - { REG_SPI4_DESKEW, 0x00080000 }, - { REG_SPI4_ING_SETUP2, 0x08080004 }, - { REG_SPI4_ING_SETUP0, 0x04111004 }, - { REG_SPI4_EGR_SETUP0, 0x80001a04 }, - { REG_SPI4_ING_SETUP1, 0x02010000 }, - { REG_AGE_INC(0), 0x00000000 }, - { REG_AGE_INC(1), 0x00000000 }, - { REG_ING_CONTROL, 0x0a200011 }, - { REG_EGR_CONTROL, 0xa0010091 }, -}; - -static struct init_table vsc7326_portinit[4][22] = { - { /* Port 0 */ - /* FIFO setup */ - { REG_DBG(0), 0x000004f0 }, - { REG_HDX(0), 0x00073101 }, - { REG_TEST(0,0), 0x00000022 }, - { REG_TEST(1,0), 0x00000022 }, - { REG_TOP_BOTTOM(0,0), 0x003f0000 }, - { REG_TOP_BOTTOM(1,0), 0x00120000 }, - { REG_HIGH_LOW_WM(0,0), 0x07460757 }, - { REG_HIGH_LOW_WM(1,0), WM_DISABLE }, - { REG_CT_THRHLD(0,0), 0x00000000 }, - { REG_CT_THRHLD(1,0), 0x00000000 }, - { REG_BUCKE(0), 0x0002ffff }, - { REG_BUCKI(0), 0x0002ffff }, - { REG_TEST(0,0), 0x00000020 }, - { REG_TEST(1,0), 0x00000020 }, - /* Port config */ - { REG_MAX_LEN(0), 0x00002710 }, - { REG_PORT_FAIL(0), 0x00000002 }, - { REG_NORMALIZER(0), 0x00000a64 }, - { REG_DENORM(0), 0x00000010 }, - { REG_STICK_BIT(0), 0x03baa370 }, - { REG_DEV_SETUP(0), 0x00000083 }, - { REG_DEV_SETUP(0), 0x00000082 }, - { REG_MODE_CFG(0), 0x0200259f }, - }, - { /* Port 1 */ - /* FIFO setup */ - { REG_DBG(1), 0x000004f0 }, - { REG_HDX(1), 0x00073101 }, - { REG_TEST(0,1), 0x00000022 }, - { REG_TEST(1,1), 0x00000022 }, - { REG_TOP_BOTTOM(0,1), 0x007e003f }, - { REG_TOP_BOTTOM(1,1), 0x00240012 }, - { REG_HIGH_LOW_WM(0,1), 0x07460757 }, - { REG_HIGH_LOW_WM(1,1), WM_DISABLE }, - { REG_CT_THRHLD(0,1), 0x00000000 }, - { REG_CT_THRHLD(1,1), 0x00000000 }, - { REG_BUCKE(1), 0x0002ffff }, - { REG_BUCKI(1), 0x0002ffff }, - { REG_TEST(0,1), 0x00000020 }, - { REG_TEST(1,1), 0x00000020 }, - /* Port config */ - { REG_MAX_LEN(1), 0x00002710 }, - { REG_PORT_FAIL(1), 0x00000002 }, - { REG_NORMALIZER(1), 0x00000a64 }, - { REG_DENORM(1), 0x00000010 }, - { REG_STICK_BIT(1), 0x03baa370 }, - { REG_DEV_SETUP(1), 0x00000083 }, - { REG_DEV_SETUP(1), 0x00000082 }, - { REG_MODE_CFG(1), 0x0200259f }, - }, - { /* Port 2 */ - /* FIFO setup */ - { REG_DBG(2), 0x000004f0 }, - { REG_HDX(2), 0x00073101 }, - { REG_TEST(0,2), 0x00000022 }, - { REG_TEST(1,2), 0x00000022 }, - { REG_TOP_BOTTOM(0,2), 0x00bd007e }, - { REG_TOP_BOTTOM(1,2), 0x00360024 }, - { REG_HIGH_LOW_WM(0,2), 0x07460757 }, - { REG_HIGH_LOW_WM(1,2), WM_DISABLE }, - { REG_CT_THRHLD(0,2), 0x00000000 }, - { REG_CT_THRHLD(1,2), 0x00000000 }, - { REG_BUCKE(2), 0x0002ffff }, - { REG_BUCKI(2), 0x0002ffff }, - { REG_TEST(0,2), 0x00000020 }, - { REG_TEST(1,2), 0x00000020 }, - /* Port config */ - { REG_MAX_LEN(2), 0x00002710 }, - { REG_PORT_FAIL(2), 0x00000002 }, - { REG_NORMALIZER(2), 0x00000a64 }, - { REG_DENORM(2), 0x00000010 }, - { REG_STICK_BIT(2), 0x03baa370 }, - { REG_DEV_SETUP(2), 0x00000083 }, - { REG_DEV_SETUP(2), 0x00000082 }, - { REG_MODE_CFG(2), 0x0200259f }, - }, - { /* Port 3 */ - /* FIFO setup */ - { REG_DBG(3), 0x000004f0 }, - { REG_HDX(3), 0x00073101 }, - { REG_TEST(0,3), 0x00000022 }, - { REG_TEST(1,3), 0x00000022 }, - { REG_TOP_BOTTOM(0,3), 0x00fc00bd }, - { REG_TOP_BOTTOM(1,3), 0x00480036 }, - { REG_HIGH_LOW_WM(0,3), 0x07460757 }, - { REG_HIGH_LOW_WM(1,3), WM_DISABLE }, - { REG_CT_THRHLD(0,3), 0x00000000 }, - { REG_CT_THRHLD(1,3), 0x00000000 }, - { REG_BUCKE(3), 0x0002ffff }, - { REG_BUCKI(3), 0x0002ffff }, - { REG_TEST(0,3), 0x00000020 }, - { REG_TEST(1,3), 0x00000020 }, - /* Port config */ - { REG_MAX_LEN(3), 0x00002710 }, - { REG_PORT_FAIL(3), 0x00000002 }, - { REG_NORMALIZER(3), 0x00000a64 }, - { REG_DENORM(3), 0x00000010 }, - { REG_STICK_BIT(3), 0x03baa370 }, - { REG_DEV_SETUP(3), 0x00000083 }, - { REG_DEV_SETUP(3), 0x00000082 }, - { REG_MODE_CFG(3), 0x0200259f }, - }, -}; - -static void run_table(adapter_t *adapter, struct init_table *ib, int len) -{ - int i; - - for (i = 0; i < len; i++) { - if (ib[i].addr == INITBLOCK_SLEEP) { - udelay( ib[i].data ); - pr_err("sleep %d us\n",ib[i].data); - } else - vsc_write( adapter, ib[i].addr, ib[i].data ); - } -} - -static int bist_rd(adapter_t *adapter, int moduleid, int address) -{ - int data = 0; - u32 result = 0; - - if ((address != 0x0) && - (address != 0x1) && - (address != 0x2) && - (address != 0xd) && - (address != 0xe)) - pr_err("No bist address: 0x%x\n", address); - - data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) | - ((moduleid & 0xff) << 0)); - vsc_write(adapter, REG_RAM_BIST_CMD, data); - - udelay(10); - - vsc_read(adapter, REG_RAM_BIST_RESULT, &result); - if ((result & (1 << 9)) != 0x0) - pr_err("Still in bist read: 0x%x\n", result); - else if ((result & (1 << 8)) != 0x0) - pr_err("bist read error: 0x%x\n", result); - - return result & 0xff; -} - -static int bist_wr(adapter_t *adapter, int moduleid, int address, int value) -{ - int data = 0; - u32 result = 0; - - if ((address != 0x0) && - (address != 0x1) && - (address != 0x2) && - (address != 0xd) && - (address != 0xe)) - pr_err("No bist address: 0x%x\n", address); - - if (value > 255) - pr_err("Suspicious write out of range value: 0x%x\n", value); - - data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) | - ((moduleid & 0xff) << 0)); - vsc_write(adapter, REG_RAM_BIST_CMD, data); - - udelay(5); - - vsc_read(adapter, REG_RAM_BIST_CMD, &result); - if ((result & (1 << 27)) != 0x0) - pr_err("Still in bist write: 0x%x\n", result); - else if ((result & (1 << 26)) != 0x0) - pr_err("bist write error: 0x%x\n", result); - - return 0; -} - -static int run_bist(adapter_t *adapter, int moduleid) -{ - /*run bist*/ - (void) bist_wr(adapter,moduleid, 0x00, 0x02); - (void) bist_wr(adapter,moduleid, 0x01, 0x01); - - return 0; -} - -static int check_bist(adapter_t *adapter, int moduleid) -{ - int result=0; - int column=0; - /*check bist*/ - result = bist_rd(adapter,moduleid, 0x02); - column = ((bist_rd(adapter,moduleid, 0x0e)<<8) + - (bist_rd(adapter,moduleid, 0x0d))); - if ((result & 3) != 0x3) - pr_err("Result: 0x%x BIST error in ram %d, column: 0x%04x\n", - result, moduleid, column); - return 0; -} - -static int enable_mem(adapter_t *adapter, int moduleid) -{ - /*enable mem*/ - (void) bist_wr(adapter,moduleid, 0x00, 0x00); - return 0; -} - -static int run_bist_all(adapter_t *adapter) -{ - int port = 0; - u32 val = 0; - - vsc_write(adapter, REG_MEM_BIST, 0x5); - vsc_read(adapter, REG_MEM_BIST, &val); - - for (port = 0; port < 12; port++) - vsc_write(adapter, REG_DEV_SETUP(port), 0x0); - - udelay(300); - vsc_write(adapter, REG_SPI4_MISC, 0x00040409); - udelay(300); - - (void) run_bist(adapter,13); - (void) run_bist(adapter,14); - (void) run_bist(adapter,20); - (void) run_bist(adapter,21); - mdelay(200); - (void) check_bist(adapter,13); - (void) check_bist(adapter,14); - (void) check_bist(adapter,20); - (void) check_bist(adapter,21); - udelay(100); - (void) enable_mem(adapter,13); - (void) enable_mem(adapter,14); - (void) enable_mem(adapter,20); - (void) enable_mem(adapter,21); - udelay(300); - vsc_write(adapter, REG_SPI4_MISC, 0x60040400); - udelay(300); - for (port = 0; port < 12; port++) - vsc_write(adapter, REG_DEV_SETUP(port), 0x1); - - udelay(300); - vsc_write(adapter, REG_MEM_BIST, 0x0); - mdelay(10); - return 0; -} - -static int mac_intr_handler(struct cmac *mac) -{ - return 0; -} - -static int mac_intr_enable(struct cmac *mac) -{ - return 0; -} - -static int mac_intr_disable(struct cmac *mac) -{ - return 0; -} - -static int mac_intr_clear(struct cmac *mac) -{ - return 0; -} - -/* Expect MAC address to be in network byte order. */ -static int mac_set_address(struct cmac* mac, u8 addr[6]) -{ - u32 val; - int port = mac->instance->index; - - vsc_write(mac->adapter, REG_MAC_LOW_ADDR(port), - (addr[3] << 16) | (addr[4] << 8) | addr[5]); - vsc_write(mac->adapter, REG_MAC_HIGH_ADDR(port), - (addr[0] << 16) | (addr[1] << 8) | addr[2]); - - vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &val); - val &= ~0xf0000000; - vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, val | (port << 28)); - - vsc_write(mac->adapter, REG_ING_FFILT_MASK0, - 0xffff0000 | (addr[4] << 8) | addr[5]); - vsc_write(mac->adapter, REG_ING_FFILT_MASK1, - 0xffff0000 | (addr[2] << 8) | addr[3]); - vsc_write(mac->adapter, REG_ING_FFILT_MASK2, - 0xffff0000 | (addr[0] << 8) | addr[1]); - return 0; -} - -static int mac_get_address(struct cmac *mac, u8 addr[6]) -{ - u32 addr_lo, addr_hi; - int port = mac->instance->index; - - vsc_read(mac->adapter, REG_MAC_LOW_ADDR(port), &addr_lo); - vsc_read(mac->adapter, REG_MAC_HIGH_ADDR(port), &addr_hi); - - addr[0] = (u8) (addr_hi >> 16); - addr[1] = (u8) (addr_hi >> 8); - addr[2] = (u8) addr_hi; - addr[3] = (u8) (addr_lo >> 16); - addr[4] = (u8) (addr_lo >> 8); - addr[5] = (u8) addr_lo; - return 0; -} - -/* This is intended to reset a port, not the whole MAC */ -static int mac_reset(struct cmac *mac) -{ - int index = mac->instance->index; - - run_table(mac->adapter, vsc7326_portinit[index], - ARRAY_SIZE(vsc7326_portinit[index])); - - return 0; -} - -static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm) -{ - u32 v; - int port = mac->instance->index; - - vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &v); - v |= 1 << 12; - - if (t1_rx_mode_promisc(rm)) - v &= ~(1 << (port + 16)); - else - v |= 1 << (port + 16); - - vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, v); - return 0; -} - -static int mac_set_mtu(struct cmac *mac, int mtu) -{ - int port = mac->instance->index; - - if (mtu > MAX_MTU) - return -EINVAL; - - /* max_len includes header and FCS */ - vsc_write(mac->adapter, REG_MAX_LEN(port), mtu + 14 + 4); - return 0; -} - -static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, - int fc) -{ - u32 v; - int enable, port = mac->instance->index; - - if (speed >= 0 && speed != SPEED_10 && speed != SPEED_100 && - speed != SPEED_1000) - return -1; - if (duplex > 0 && duplex != DUPLEX_FULL) - return -1; - - if (speed >= 0) { - vsc_read(mac->adapter, REG_MODE_CFG(port), &v); - enable = v & 3; /* save tx/rx enables */ - v &= ~0xf; - v |= 4; /* full duplex */ - if (speed == SPEED_1000) - v |= 8; /* GigE */ - enable |= v; - vsc_write(mac->adapter, REG_MODE_CFG(port), v); - - if (speed == SPEED_1000) - v = 0x82; - else if (speed == SPEED_100) - v = 0x84; - else /* SPEED_10 */ - v = 0x86; - vsc_write(mac->adapter, REG_DEV_SETUP(port), v | 1); /* reset */ - vsc_write(mac->adapter, REG_DEV_SETUP(port), v); - vsc_read(mac->adapter, REG_DBG(port), &v); - v &= ~0xff00; - if (speed == SPEED_1000) - v |= 0x400; - else if (speed == SPEED_100) - v |= 0x2000; - else /* SPEED_10 */ - v |= 0xff00; - vsc_write(mac->adapter, REG_DBG(port), v); - - vsc_write(mac->adapter, REG_TX_IFG(port), - speed == SPEED_1000 ? 5 : 0x11); - if (duplex == DUPLEX_HALF) - enable = 0x0; /* 100 or 10 */ - else if (speed == SPEED_1000) - enable = 0xc; - else /* SPEED_100 or 10 */ - enable = 0x4; - enable |= 0x9 << 10; /* IFG1 */ - enable |= 0x6 << 6; /* IFG2 */ - enable |= 0x1 << 4; /* VLAN */ - enable |= 0x3; /* RX/TX EN */ - vsc_write(mac->adapter, REG_MODE_CFG(port), enable); - - } - - vsc_read(mac->adapter, REG_PAUSE_CFG(port), &v); - v &= 0xfff0ffff; - v |= 0x20000; /* xon/xoff */ - if (fc & PAUSE_RX) - v |= 0x40000; - if (fc & PAUSE_TX) - v |= 0x80000; - if (fc == (PAUSE_RX | PAUSE_TX)) - v |= 0x10000; - vsc_write(mac->adapter, REG_PAUSE_CFG(port), v); - return 0; -} - -static int mac_enable(struct cmac *mac, int which) -{ - u32 val; - int port = mac->instance->index; - - /* Write the correct WM value when the port is enabled. */ - vsc_write(mac->adapter, REG_HIGH_LOW_WM(1,port), WM_ENABLE); - - vsc_read(mac->adapter, REG_MODE_CFG(port), &val); - if (which & MAC_DIRECTION_RX) - val |= 0x2; - if (which & MAC_DIRECTION_TX) - val |= 1; - vsc_write(mac->adapter, REG_MODE_CFG(port), val); - return 0; -} - -static int mac_disable(struct cmac *mac, int which) -{ - u32 val; - int i, port = mac->instance->index; - - /* Reset the port, this also writes the correct WM value */ - mac_reset(mac); - - vsc_read(mac->adapter, REG_MODE_CFG(port), &val); - if (which & MAC_DIRECTION_RX) - val &= ~0x2; - if (which & MAC_DIRECTION_TX) - val &= ~0x1; - vsc_write(mac->adapter, REG_MODE_CFG(port), val); - vsc_read(mac->adapter, REG_MODE_CFG(port), &val); - - /* Clear stats */ - for (i = 0; i <= 0x3a; ++i) - vsc_write(mac->adapter, CRA(4, port, i), 0); - - /* Clear software counters */ - memset(&mac->stats, 0, sizeof(struct cmac_statistics)); - - return 0; -} - -static void rmon_update(struct cmac *mac, unsigned int addr, u64 *stat) -{ - u32 v, lo; - - vsc_read(mac->adapter, addr, &v); - lo = *stat; - *stat = *stat - lo + v; - - if (v == 0) - return; - - if (v < lo) - *stat += (1ULL << 32); -} - -static void port_stats_update(struct cmac *mac) -{ - struct { - unsigned int reg; - unsigned int offset; - } hw_stats[] = { - -#define HW_STAT(reg, stat_name) \ - { reg, (&((struct cmac_statistics *)NULL)->stat_name) - (u64 *)NULL } - - /* Rx stats */ - HW_STAT(RxUnicast, RxUnicastFramesOK), - HW_STAT(RxMulticast, RxMulticastFramesOK), - HW_STAT(RxBroadcast, RxBroadcastFramesOK), - HW_STAT(Crc, RxFCSErrors), - HW_STAT(RxAlignment, RxAlignErrors), - HW_STAT(RxOversize, RxFrameTooLongErrors), - HW_STAT(RxPause, RxPauseFrames), - HW_STAT(RxJabbers, RxJabberErrors), - HW_STAT(RxFragments, RxRuntErrors), - HW_STAT(RxUndersize, RxRuntErrors), - HW_STAT(RxSymbolCarrier, RxSymbolErrors), - HW_STAT(RxSize1519ToMax, RxJumboFramesOK), - - /* Tx stats (skip collision stats as we are full-duplex only) */ - HW_STAT(TxUnicast, TxUnicastFramesOK), - HW_STAT(TxMulticast, TxMulticastFramesOK), - HW_STAT(TxBroadcast, TxBroadcastFramesOK), - HW_STAT(TxPause, TxPauseFrames), - HW_STAT(TxUnderrun, TxUnderrun), - HW_STAT(TxSize1519ToMax, TxJumboFramesOK), - }, *p = hw_stats; - unsigned int port = mac->instance->index; - u64 *stats = (u64 *)&mac->stats; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(hw_stats); i++) - rmon_update(mac, CRA(0x4, port, p->reg), stats + p->offset); - - rmon_update(mac, REG_TX_OK_BYTES(port), &mac->stats.TxOctetsOK); - rmon_update(mac, REG_RX_OK_BYTES(port), &mac->stats.RxOctetsOK); - rmon_update(mac, REG_RX_BAD_BYTES(port), &mac->stats.RxOctetsBad); -} - -/* - * This function is called periodically to accumulate the current values of the - * RMON counters into the port statistics. Since the counters are only 32 bits - * some of them can overflow in less than a minute at GigE speeds, so this - * function should be called every 30 seconds or so. - * - * To cut down on reading costs we update only the octet counters at each tick - * and do a full update at major ticks, which can be every 30 minutes or more. - */ -static const struct cmac_statistics *mac_update_statistics(struct cmac *mac, - int flag) -{ - if (flag == MAC_STATS_UPDATE_FULL || - mac->instance->ticks >= MAJOR_UPDATE_TICKS) { - port_stats_update(mac); - mac->instance->ticks = 0; - } else { - int port = mac->instance->index; - - rmon_update(mac, REG_RX_OK_BYTES(port), - &mac->stats.RxOctetsOK); - rmon_update(mac, REG_RX_BAD_BYTES(port), - &mac->stats.RxOctetsBad); - rmon_update(mac, REG_TX_OK_BYTES(port), - &mac->stats.TxOctetsOK); - mac->instance->ticks++; - } - return &mac->stats; -} - -static void mac_destroy(struct cmac *mac) -{ - kfree(mac); -} - -static struct cmac_ops vsc7326_ops = { - .destroy = mac_destroy, - .reset = mac_reset, - .interrupt_handler = mac_intr_handler, - .interrupt_enable = mac_intr_enable, - .interrupt_disable = mac_intr_disable, - .interrupt_clear = mac_intr_clear, - .enable = mac_enable, - .disable = mac_disable, - .set_mtu = mac_set_mtu, - .set_rx_mode = mac_set_rx_mode, - .set_speed_duplex_fc = mac_set_speed_duplex_fc, - .statistics_update = mac_update_statistics, - .macaddress_get = mac_get_address, - .macaddress_set = mac_set_address, -}; - -static struct cmac *vsc7326_mac_create(adapter_t *adapter, int index) -{ - struct cmac *mac; - u32 val; - int i; - - mac = kzalloc(sizeof(*mac) + sizeof(cmac_instance), GFP_KERNEL); - if (!mac) - return NULL; - - mac->ops = &vsc7326_ops; - mac->instance = (cmac_instance *)(mac + 1); - mac->adapter = adapter; - - mac->instance->index = index; - mac->instance->ticks = 0; - - i = 0; - do { - u32 vhi, vlo; - - vhi = vlo = 0; - t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo); - udelay(1); - t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi); - udelay(5); - val = (vhi << 16) | vlo; - } while ((++i < 10000) && (val == 0xffffffff)); - - return mac; -} - -static int vsc7326_mac_reset(adapter_t *adapter) -{ - vsc7326_full_reset(adapter); - (void) run_bist_all(adapter); - run_table(adapter, vsc7326_reset, ARRAY_SIZE(vsc7326_reset)); - return 0; -} - -const struct gmac t1_vsc7326_ops = { - .stats_update_period = STATS_TICK_SECS, - .create = vsc7326_mac_create, - .reset = vsc7326_mac_reset, -}; diff --git a/drivers/net/chelsio/vsc7326_reg.h b/drivers/net/chelsio/vsc7326_reg.h deleted file mode 100644 index 479edbcabe6..00000000000 --- a/drivers/net/chelsio/vsc7326_reg.h +++ /dev/null @@ -1,297 +0,0 @@ -/* $Date: 2006/04/28 19:20:17 $ $RCSfile: vsc7326_reg.h,v $ $Revision: 1.5 $ */ -#ifndef _VSC7321_REG_H_ -#define _VSC7321_REG_H_ - -/* Register definitions for Vitesse VSC7321 (Meigs II) MAC - * - * Straight off the data sheet, VMDS-10038 Rev 2.0 and - * PD0011-01-14-Meigs-II 2002-12-12 - */ - -/* Just 'cause it's in here doesn't mean it's used. */ - -#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1)) - -/* System and CPU comm's registers */ -#define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */ -#define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */ -#define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */ -#define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */ -#define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */ -#define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */ -#define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */ -#define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */ -#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */ -#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */ -#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */ -#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */ -#define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */ -#define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */ -#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */ -#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */ -#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */ - -/* Aggregator registers */ -#define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */ -#define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */ -#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */ -#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */ -#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */ -#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */ -#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */ -#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */ -#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */ -#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */ -#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */ -#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */ - -/* BIST registers */ -/*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */ -/*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */ -#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */ -#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */ -#define BIST_PORT_SELECT 0x00 /* BIST port select */ -#define BIST_COMMAND 0x01 /* BIST enable/disable */ -#define BIST_STATUS 0x02 /* BIST operation status */ -#define BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */ -#define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */ -#define BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */ -#define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */ -#define BIST_ERROR_STATE 0x07 /* BIST engine internal state */ -#define BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */ -#define BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */ -#define BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */ -#define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */ - -/* FIFO registers - * ie = 0 for ingress, 1 for egress - * fn = FIFO number, 0-9 - */ -#define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */ -#define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */ -#define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */ -#define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */ -#define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */ -#define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */ -#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */ -#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */ -#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */ -#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */ - -/* Traffic shaper buckets - * ie = 0 for ingress, 1 for egress - * bn = bucket number 0-10 (yes, 11 buckets) - */ -/* OK, this one's kinda ugly. Some hardware designers are perverse. */ -#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4)) -#define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b) - -#define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */ -#define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */ -#define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */ -#define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */ -#define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */ -#define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */ -#define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */ -#define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */ -/* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */ -#define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */ -#define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */ -#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */ -#define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */ -#define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */ -#define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */ -#define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */ - -/* SPI4 interface */ -#define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */ -#define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */ -#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */ -#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */ -#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */ -#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */ -#define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */ -#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */ -#define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */ -#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */ -#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */ -#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */ -#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */ -#define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */ -#define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */ -#define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */ -#define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */ -#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */ -#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */ -#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */ - -#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */ - -/* 10GbE MAC Block Registers */ -/* Note that those registers that are exactly the same for 10GbE as for - * tri-speed are only defined with the version that needs a port number. - * Pass 0xa in those cases. - * - * Also note that despite the presence of a MAC address register, this part - * does no ingress MAC address filtering. That register is used only for - * pause frame detection and generation. - */ -/* 10GbE specific, and different from tri-speed */ -#define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */ -#define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */ -#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */ -#define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */ -#define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */ -#define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */ -#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */ -#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */ -#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */ -#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */ -#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */ -#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */ -#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */ -#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */ -#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */ -#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */ -#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */ -#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */ -#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */ -#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */ -#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */ -#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */ -#define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */ - -/* pn = port number 0-9 for tri-speed, 10 for 10GbE */ -/* Both tri-speed and 10GbE */ -#define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */ -#define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */ -#define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */ - -/* tri-speed only - * pn = port number, 0-9 - */ -#define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */ -#define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */ -#define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */ -#define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */ -#define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */ -#define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */ -#define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */ -#define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */ -#define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */ -#define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */ -#define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */ -#define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */ -#define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */ -#define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */ -#define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */ -#define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */ -#define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */ -#define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */ -#define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */ -#define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */ - -/* Statistics */ -/* CRA(0x4,pn,reg) */ -/* reg below */ -/* pn = port number, 0-a, a = 10GbE */ - -enum { - RxInBytes = 0x00, // # Rx in octets - RxSymbolCarrier = 0x01, // Frames w/ symbol errors - RxPause = 0x02, // # pause frames received - RxUnsupOpcode = 0x03, // # control frames with unsupported opcode - RxOkBytes = 0x04, // # octets in good frames - RxBadBytes = 0x05, // # octets in bad frames - RxUnicast = 0x06, // # good unicast frames - RxMulticast = 0x07, // # good multicast frames - RxBroadcast = 0x08, // # good broadcast frames - Crc = 0x09, // # frames w/ bad CRC only - RxAlignment = 0x0a, // # frames w/ alignment err - RxUndersize = 0x0b, // # frames undersize - RxFragments = 0x0c, // # frames undersize w/ crc err - RxInRangeLengthError = 0x0d, // # frames with length error - RxOutOfRangeError = 0x0e, // # frames with illegal length field - RxOversize = 0x0f, // # frames oversize - RxJabbers = 0x10, // # frames oversize w/ crc err - RxSize64 = 0x11, // # frames 64 octets long - RxSize65To127 = 0x12, // # frames 65-127 octets - RxSize128To255 = 0x13, // # frames 128-255 - RxSize256To511 = 0x14, // # frames 256-511 - RxSize512To1023 = 0x15, // # frames 512-1023 - RxSize1024To1518 = 0x16, // # frames 1024-1518 - RxSize1519ToMax = 0x17, // # frames 1519-max - - TxOutBytes = 0x18, // # octets tx - TxPause = 0x19, // # pause frames sent - TxOkBytes = 0x1a, // # octets tx OK - TxUnicast = 0x1b, // # frames unicast - TxMulticast = 0x1c, // # frames multicast - TxBroadcast = 0x1d, // # frames broadcast - TxMultipleColl = 0x1e, // # frames tx after multiple collisions - TxLateColl = 0x1f, // # late collisions detected - TxXcoll = 0x20, // # frames lost, excessive collisions - TxDefer = 0x21, // # frames deferred on first tx attempt - TxXdefer = 0x22, // # frames excessively deferred - TxCsense = 0x23, // carrier sense errors at frame end - TxSize64 = 0x24, // # frames 64 octets long - TxSize65To127 = 0x25, // # frames 65-127 octets - TxSize128To255 = 0x26, // # frames 128-255 - TxSize256To511 = 0x27, // # frames 256-511 - TxSize512To1023 = 0x28, // # frames 512-1023 - TxSize1024To1518 = 0x29, // # frames 1024-1518 - TxSize1519ToMax = 0x2a, // # frames 1519-max - TxSingleColl = 0x2b, // # frames tx after single collision - TxBackoff2 = 0x2c, // # frames tx ok after 2 backoffs/collisions - TxBackoff3 = 0x2d, // after 3 backoffs/collisions - TxBackoff4 = 0x2e, // after 4 - TxBackoff5 = 0x2f, // after 5 - TxBackoff6 = 0x30, // after 6 - TxBackoff7 = 0x31, // after 7 - TxBackoff8 = 0x32, // after 8 - TxBackoff9 = 0x33, // after 9 - TxBackoff10 = 0x34, // after 10 - TxBackoff11 = 0x35, // after 11 - TxBackoff12 = 0x36, // after 12 - TxBackoff13 = 0x37, // after 13 - TxBackoff14 = 0x38, // after 14 - TxBackoff15 = 0x39, // after 15 - TxUnderrun = 0x3a, // # frames dropped from underrun - // Hole. See REG_RX_XGMII_PROT_ERR below. - RxIpgShrink = 0x3c, // # of IPG shrinks detected - // Duplicate. See REG_STAT_STICKY10G below. - StatSticky1G = 0x3e, // tri-speed sticky bits - StatInit = 0x3f // Clear all statistics -}; - -#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */ -#define REG_STAT_STICKY10G CRA(0x4,0xa,StatSticky1G) /* 10GbE sticky bits */ - -#define REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes) -#define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,RxBadBytes) -#define REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes) - -/* MII-Management Block registers */ -/* These are for MII-M interface 0, which is the bidirectional LVTTL one. If - * we hooked up to the one with separate directions, the middle 0x0 needs to - * change to 0x1. And the current errata states that MII-M 1 doesn't work. - */ - -#define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */ -#define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */ -#define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */ -#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */ - -#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd) -#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d) -#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d) -#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d) -#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d) -#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d) -#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d) -#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d) - - -/* Whew. */ - -#endif |