diff options
| author | Divy Le Ray <divy@chelsio.com> | 2007-05-30 21:10:58 -0700 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2007-07-08 22:16:39 -0400 |
| commit | 480fe1a31c662ef4ff0598a7cacefa21f98335f1 (patch) | |
| tree | 66da8f259d7093d7f9290054f4fbda1f68ff9e0a /drivers/net/cxgb3/regs.h | |
| parent | 8a9fab22cf6a3abde7731f4425d4ff87509bc15a (diff) | |
cxgb3 - TP SRAM update
The chip executes microcode present in internal RAM,
whose content is loaded from EEPROM on power cycle.
This patch allows an update of the microcode through PIO
without forcing a power cycle.
Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/cxgb3/regs.h')
| -rw-r--r-- | drivers/net/cxgb3/regs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h index 02f8731ffb0..aa80313c922 100644 --- a/drivers/net/cxgb3/regs.h +++ b/drivers/net/cxgb3/regs.h @@ -1218,6 +1218,13 @@ #define A_TP_PROXY_FLOW_CNTL 0x4b0 +#define A_TP_EMBED_OP_FIELD0 0x4e8 +#define A_TP_EMBED_OP_FIELD1 0x4ec +#define A_TP_EMBED_OP_FIELD2 0x4f0 +#define A_TP_EMBED_OP_FIELD3 0x4f4 +#define A_TP_EMBED_OP_FIELD4 0x4f8 +#define A_TP_EMBED_OP_FIELD5 0x4fc + #define A_ULPRX_CTL 0x500 #define S_ROUND_ROBIN 4 |