diff options
| author | David S. Miller <davem@davemloft.net> | 2011-08-20 10:39:12 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-08-20 10:39:12 -0700 |
| commit | 823dcd2506fa369aeb8cbd26da5663efe2fda9a9 (patch) | |
| tree | 853b3e3c05f0b9ee1b5df8464db19b7acc57150c /drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | |
| parent | eaa36660de7e174498618d69d7277d44a2f24c3d (diff) | |
| parent | 98e77438aed3cd3343cbb86825127b1d9d2bea33 (diff) | |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c')
| -rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index f4ab90c2089..72047899395 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c @@ -5794,6 +5794,12 @@ static int bnx2x_init_hw_common(struct bnx2x *bp) DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); + /* + * take the UNDI lock to protect undi_unload flow from accessing + * registers while we're resetting the chip + */ + bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); + bnx2x_reset_common(bp); REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); @@ -5804,6 +5810,8 @@ static int bnx2x_init_hw_common(struct bnx2x *bp) } REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); + bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); + bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); if (!CHIP_IS_E1x(bp)) { @@ -10245,10 +10253,17 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev, /* clean indirect addresses */ pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET); - REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0); - REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0); - REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0); - REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0); + /* Clean the following indirect addresses for all functions since it + * is not used by the driver. + */ + REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); + REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); + REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); + REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); + REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); + REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); + REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); + REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); /* * Enable internal target-read (in case we are probed after PF FLR). |