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authorRoland Dreier <roland@purestorage.com>2014-04-28 17:36:20 -0700
committerDavid S. Miller <davem@davemloft.net>2014-04-30 16:12:21 -0400
commitd2e752db6d05374a35dddb2e17864fe310fbcf69 (patch)
tree43cb815f741bff8a2f26136541a261785aabcbb9 /drivers/net/ethernet/chelsio/cxgb4
parent652f99ead8319941216c64d7f92c8dcdc9b95970 (diff)
cxgb4: Decode PCIe Gen3 link speed
Add handling for " 8 GT/s" in print_port_info(). Signed-off-by: Roland Dreier <roland@purestorage.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 6fe58913403..24e16e3301e 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -5870,6 +5870,8 @@ static void print_port_info(const struct net_device *dev)
spd = " 2.5 GT/s";
else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
spd = " 5 GT/s";
+ else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
+ spd = " 8 GT/s";
if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
bufp += sprintf(bufp, "100/");