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authorVasu Dev <vasu.dev@intel.com>2011-05-11 05:41:46 +0000
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-06-21 01:22:44 -0700
commitdadbe85ac47f180fa1e3ef93b276ab7938b1a98b (patch)
treee2e6924ffa0c510e6ee246184593b82783c8c75a /drivers/net/fealnx.c
parent9612de92e023bff0d1cd5725ee65293accc70c56 (diff)
ixgbe: setup per CPU PCI pool for FCoE DDP
Currently single PCI pool used across all CPUs and that doesn't scales up as number of CPU increases, so this patch adds per CPU PCI pool to setup udl and that aligns well from FCoE stack as that already has per CPU exch locking. Adds per CPU PCI alloc setup and free in ixgbe_fcoe_ddp_pools_alloc and ixgbe_fcoe_ddp_pools_free, use CPU specific pool during DDP setup. Re-arranged ixgbe_fcoe struct to have fewer holes along with adding pools ptr using pahole. Signed-off-by: Vasu Dev <vasu.dev@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/fealnx.c')
0 files changed, 0 insertions, 0 deletions