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authorPJ Waskiewicz <peter.p.waskiewicz.jr@intel.com>2009-03-25 22:10:42 +0000
committerDavid S. Miller <davem@davemloft.net>2009-03-26 01:13:51 -0700
commitbb3daa4a5960cd9d39bad88679fcf587b456c05d (patch)
tree31cbdf87fed0af126ff0c3e0647dfa90aab8a7c7 /drivers/net/ixgbe/ixgbe_common.c
parentede5ad0e29b641c3d3a644272a9127bfd98dfcc8 (diff)
ixgbe: Allow Priority Flow Control settings to survive a device reset
When changing DCB parameters, ixgbe needs to have the MAC reset. The way the flow control code is setup today, PFC will be disabled on a reset. This patch adds a new flow control type for PFC, and then has the netlink layer take care of toggling which type of flow control to enable. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_common.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c23
1 files changed, 21 insertions, 2 deletions
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index 245db0e712e..8cfd3fd309a 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -1654,9 +1654,10 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames,
* but not send pause frames).
- * 2: Tx flow control is enabled (we can send pause frames but
- * we do not support receiving pause frames).
+ * 2: Tx flow control is enabled (we can send pause frames but
+ * we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
+ * 4: Priority Flow Control is enabled.
* other: Invalid.
*/
switch (hw->fc.current_mode) {
@@ -1686,6 +1687,11 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
mflcn_reg |= IXGBE_MFLCN_RFCE;
fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
break;
+#ifdef CONFIG_DCB
+ case ixgbe_fc_pfc:
+ goto out;
+ break;
+#endif
default:
hw_dbg(hw, "Flow control param set incorrectly\n");
ret_val = -IXGBE_ERR_CONFIG;
@@ -1746,6 +1752,7 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
* 2: Tx flow control is enabled (we can send pause frames but
* we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
+ * 4: Priority Flow Control is enabled.
* other: Invalid.
*/
switch (hw->fc.current_mode) {
@@ -1776,6 +1783,11 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
/* Flow control (both Rx and Tx) is enabled by SW override. */
reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
break;
+#ifdef CONFIG_DCB
+ case ixgbe_fc_pfc:
+ goto out;
+ break;
+#endif
default:
hw_dbg(hw, "Flow control param set incorrectly\n");
ret_val = -IXGBE_ERR_CONFIG;
@@ -1874,6 +1886,13 @@ s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
ixgbe_link_speed speed;
bool link_up;
+#ifdef CONFIG_DCB
+ if (hw->fc.requested_mode == ixgbe_fc_pfc) {
+ hw->fc.current_mode = hw->fc.requested_mode;
+ goto out;
+ }
+
+#endif
/* Validate the packetbuf configuration */
if (packetbuf_num < 0 || packetbuf_num > 7) {
hw_dbg(hw, "Invalid packet buffer number [%d], expected range "