diff options
| author | John Fastabend <john.r.fastabend@intel.com> | 2011-02-23 05:58:19 +0000 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2011-03-12 04:12:54 -0800 |
| commit | 17049d30c2dec6f26d6165cc135578f9e41d53d3 (patch) | |
| tree | b58a6c005d89c15a58213cc2e62e9d4de81d8c37 /drivers/net/ixgbe/ixgbe_dcb_82599.c | |
| parent | 3b97fd695453ced96f22bdf1a84453f6744d25cc (diff) | |
ixgbe: IEEE 802.1Qaz, implement priority assignment table
This patch adds support to use the priority assignment
table in the ieee_ets structure to map priorities to
traffic classes. Previously ixgbe only supported a
1:1 mapping. Now we can enable and disable hardware
DCB support when multiple traffic classes are actually
being used. This allows the default case all priorities
mapped to traffic class 0 to work in normal hardware
mode and utilize the full packet buffer.
This patch does not address putting the hardware in
4TC mode so packet buffer space may be underutilized
in this case. A follow up patch can address this
optimization. But at least we have the hooks to do
this now.
Also CEE will behave as it always has and map priorities
1:1 with traffic classes.
Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_dcb_82599.c')
| -rw-r--r-- | drivers/net/ixgbe/ixgbe_dcb_82599.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c index beaa1c1c1e6..0a482bbf1bd 100644 --- a/drivers/net/ixgbe/ixgbe_dcb_82599.c +++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c @@ -85,7 +85,8 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, - u8 *prio_type) + u8 *prio_type, + u8 *prio_tc) { u32 reg = 0; u32 credit_refill = 0; @@ -102,7 +103,7 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, /* Map all traffic classes to their UP, 1 to 1 */ reg = 0; for (i = 0; i < MAX_TRAFFIC_CLASS; i++) - reg |= (i << (i * IXGBE_RTRUP2TC_UP_SHIFT)); + reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); /* Configure traffic class credits and priority */ @@ -194,7 +195,8 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, - u8 *prio_type) + u8 *prio_type, + u8 *prio_tc) { u32 reg; u8 i; @@ -211,7 +213,7 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, /* Map all traffic classes to their UP, 1 to 1 */ reg = 0; for (i = 0; i < MAX_TRAFFIC_CLASS; i++) - reg |= (i << (i * IXGBE_RTTUP2TC_UP_SHIFT)); + reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); /* Configure traffic class credits and priority */ @@ -424,15 +426,16 @@ static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw) */ s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 rx_pba, u8 pfc_en, u16 *refill, - u16 *max, u8 *bwg_id, u8 *prio_type) + u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) { ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba); ixgbe_dcb_config_82599(hw); - ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, prio_type); + ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, + prio_type, prio_tc); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, prio_type); ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, - bwg_id, prio_type); + bwg_id, prio_type, prio_tc); ixgbe_dcb_config_pfc_82599(hw, pfc_en); ixgbe_dcb_config_tc_stats_82599(hw); |