diff options
| author | Dhananjay Phadke <dhananjay@netxen.com> | 2008-03-17 19:59:48 -0700 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2008-03-25 23:16:15 -0400 |
| commit | 443be7960be77f3345b44491c700ae4471b0fe57 (patch) | |
| tree | 48a20558ab8b4726507948b6fc3c850cac13f84b /drivers/net/netxen/netxen_nic_hdr.h | |
| parent | 9e6db60825ef7e7999abc610ce256ba768e58162 (diff) | |
netxen: improve msi support
Recent netxen firmware has new scheme of generating MSI interrupts, it
raises interrupt and blocks itself, waiting for driver to unmask. This
reduces chance of spurious interrupts.
The driver will be able to deal with older firmware as well.
Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com>
Tested-by: Vernon Mauery <mauery@us.ibm.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/netxen/netxen_nic_hdr.h')
| -rw-r--r-- | drivers/net/netxen/netxen_nic_hdr.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h index d72f8f8fcb5..160f605e58d 100644 --- a/drivers/net/netxen/netxen_nic_hdr.h +++ b/drivers/net/netxen/netxen_nic_hdr.h @@ -456,6 +456,12 @@ enum { #define ISR_INT_MASK_SLOW (NETXEN_PCIX_PS_REG(PCIX_INT_MASK)) #define ISR_INT_TARGET_STATUS (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS)) #define ISR_INT_TARGET_MASK (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK)) +#define ISR_INT_TARGET_STATUS_F1 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) +#define ISR_INT_TARGET_MASK_F1 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) +#define ISR_INT_TARGET_STATUS_F2 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) +#define ISR_INT_TARGET_MASK_F2 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) +#define ISR_INT_TARGET_STATUS_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) +#define ISR_INT_TARGET_MASK_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) #define NETXEN_PCI_MAPSIZE 128 #define NETXEN_PCI_DDR_NET (0x00000000UL) @@ -662,6 +668,12 @@ enum { #define PCIX_TARGET_STATUS (0x10118) #define PCIX_TARGET_MASK (0x10128) +#define PCIX_TARGET_STATUS_F1 (0x10160) +#define PCIX_TARGET_MASK_F1 (0x10170) +#define PCIX_TARGET_STATUS_F2 (0x10164) +#define PCIX_TARGET_MASK_F2 (0x10174) +#define PCIX_TARGET_STATUS_F3 (0x10168) +#define PCIX_TARGET_MASK_F3 (0x10178) #define PCIX_MSI_F0 (0x13000) #define PCIX_MSI_F1 (0x13004) |