diff options
| author | Alexander Duyck <alexander.h.duyck@intel.com> | 2009-05-26 13:51:05 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-05-26 20:35:06 -0700 |
| commit | cbe7a81a7370e2c4560b48e42e741bd1476bc700 (patch) | |
| tree | 06909d59a09cac98dcfd6221b67a6bcf3bf6e6ff /drivers/net/ppp_synctty.c | |
| parent | 3ea73afafb8cd237a823ec5d0a0a2f2396b03b33 (diff) | |
igb/e1000e: update PSSR_MDIX value to reflect correct bit
The phy port status register has the MDI-X status bit on bit 11, not bit 3
as is currently setup in the define. This patch corrects that so the
correct bit is checked on igp PHY types.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Acked-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ppp_synctty.c')
0 files changed, 0 insertions, 0 deletions