diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2010-01-20 16:58:02 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-01-20 19:20:57 -0800 |
| commit | 614b05900ec3516b835cd06f848ef6bc915beeea (patch) | |
| tree | be57c5d34fda094682c1ad5ff74378f40ed76113 /drivers/net/tg3.c | |
| parent | 7981d6f6b280d28779343cff4a88029fe53d1b47 (diff) | |
tg3: Enable PLL PD when CLKREQ disabled for 5717A0
PCIe PLL power down cannot be used if CLKREQ is enabled because data
corruption will occur. If CLKREQ is disabled though, enabling PCIE P1
PLL power-down saves some power.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
| -rw-r--r-- | drivers/net/tg3.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index b0630cd093a..b80e7eef8af 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -7569,6 +7569,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); } + if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) { + u32 grc_mode = tr32(GRC_MODE); + + /* Access the lower 1K of PL PCIE block registers. */ + val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; + tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); + + val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); + tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, + val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); + + tw32(GRC_MODE, grc_mode); + } + /* This works around an issue with Athlon chipsets on * B3 tigon3 silicon. This bit has no effect on any * other revision. But do not set this on PCI Express @@ -13096,6 +13110,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; + } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { + tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN; } } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |