diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2011-04-20 07:57:41 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-04-21 17:05:58 -0700 |
| commit | b4bd292933537e19107c3e151b27a15fefa5f8d0 (patch) | |
| tree | 83b0f75b02bfe670b7dfe2a24b7b749123a461dc /drivers/net/tg3.h | |
| parent | 15ee95c36d355a9f47746eaa4ae8cc0ecafec550 (diff) | |
tg3: Add write accessor for AUX CTRL phy reg
This patch adds a write accessor for the aux ctrl phy register.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index b9382f18b63..eaa76694efb 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -2197,15 +2197,19 @@ #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 +#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 +#define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 +#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 +#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12 #define MII_TG3_AUXCTL_MISC_WREN 0x8000 |