diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2009-08-25 10:07:27 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-08-26 15:47:47 -0700 |
| commit | 255ca311b650caece3ec4f78b88ef298664d561f (patch) | |
| tree | cf26fdfb0fb9f5fba78bb59a82f37abb132d4b62 /drivers/net/tg3.h | |
| parent | 521e6b90dd3f0392062845d7ef13e6e41bb99d8a (diff) | |
tg3: Prevent tx BD corruption
This patch prevents a tx BD corruption bug by preventing the device from
powering down the PLL from L1 if the link speed is 10Mbps or 100Mbps.
The same bits are also used to prevent a system hang during chip reset
resulting from a complicated set of events that ultimately leads to
PCIe block register corruption.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index c613cbb40c2..bb8591ea330 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -866,6 +866,7 @@ #define RCVLPC_STATSCTRL_ENABLE 0x00000001 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 #define RCVLPC_STATS_ENABLE 0x00002018 +#define RCVLPC_STATSENAB_ASF_FIX 0x00000002 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 #define RCVLPC_STATS_INCMASK 0x0000201c @@ -1704,7 +1705,12 @@ #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 -/* 0x7d2c --> 0x7e70 unused */ +/* 0x7d2c --> 0x7d54 unused */ + +#define TG3_PCIE_LNKCTL 0x00007d54 +#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 +#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 +/* 0x7d58 --> 0x7e70 unused */ #define TG3_PCIE_EIDLE_DELAY 0x00007e70 #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f @@ -2650,6 +2656,7 @@ struct tg3 { #define TG3_FLG3_PHY_ENABLE_APD 0x00001000 #define TG3_FLG3_5755_PLUS 0x00002000 #define TG3_FLG3_NO_NVRAM 0x00004000 +#define TG3_FLG3_TOGGLE_10_100_L1PLLPD 0x00008000 struct timer_list timer; u16 timer_counter; |