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authorHaiying Wang <Haiying.Wang@freescale.com>2009-04-29 14:14:35 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-05-19 00:50:23 -0500
commit345f84227b50e90329dd303499024603596566f4 (patch)
tree609868e873f374aacdbb58a37db8de4517bf4d8e /drivers/net/ucc_geth.h
parent06c4435021f4856261edd01e2691071edeb8fa51 (diff)
net/ucc_geth: update riscTx and riscRx in ucc_geth
Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/net/ucc_geth.h')
-rw-r--r--drivers/net/ucc_geth.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index 2f8ee7c87ef..46bb1d23359 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -1120,8 +1120,8 @@ struct ucc_geth_info {
enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
enum ucc_geth_num_of_threads numThreadsTx;
enum ucc_geth_num_of_threads numThreadsRx;
- enum qe_risc_allocation riscTx;
- enum qe_risc_allocation riscRx;
+ unsigned int riscTx;
+ unsigned int riscRx;
};
/* structure representing UCC GETH */