diff options
| author | Nick Kossifidis <mickflemm@gmail.com> | 2010-11-23 21:09:11 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-11-30 13:52:35 -0500 |
| commit | 3017fcab416d8d1ee48ca16aa9a3062f600dab8e (patch) | |
| tree | 8f6daedc2060c20a0a1a569e8e782991cd28f2a6 /drivers/net/wireless/ath/ath5k/qcu.c | |
| parent | 25ddfa195735934256fda55bb4f2d749c19386ff (diff) | |
ath5k: Extend get_default_sifs/slot_time
* Extend get_default_sifs/slot_time to include timings for turbo
half and quarter rate modes.
* AR5210 code for now uses timings already on core clock units
instead of usecs so rename them (we 'll clean it up later).
Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/qcu.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath5k/qcu.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c index c422d5c92d4..6eb6838d906 100644 --- a/drivers/net/wireless/ath/ath5k/qcu.c +++ b/drivers/net/wireless/ath/ath5k/qcu.c @@ -297,7 +297,8 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) /* Set Slot time */ ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? - AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, + AR5K_INIT_SLOT_TIME_TURBO_CLOCK : + AR5K_INIT_SLOT_TIME_CLOCK, AR5K_SLOT_TIME); /* Set ACK_CTS timeout */ ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? @@ -306,15 +307,16 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) /* Set IFS0 */ if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) { - ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + - tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO) << - AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, + ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO_CLOCK + + tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO_CLOCK) + << AR5K_IFS0_DIFS_S) | + AR5K_INIT_SIFS_TURBO_CLOCK, AR5K_IFS0); } else { - ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS + - tq->tqi_aifs * AR5K_INIT_SLOT_TIME) << + ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_CLOCK + + tq->tqi_aifs * AR5K_INIT_SLOT_TIME_CLOCK) << AR5K_IFS0_DIFS_S) | - AR5K_INIT_SIFS, AR5K_IFS0); + AR5K_INIT_SIFS_CLOCK, AR5K_IFS0); } /* Set IFS1 */ |