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authorFelix Fietkau <nbd@openwrt.org>2011-07-12 09:02:04 +0800
committerJohn W. Linville <linville@tuxdriver.com>2011-07-13 14:49:40 -0400
commit6340211c5f4775a52c98052fb5661565f79249fd (patch)
tree200d247fd75a5212330cf46785ca8a1678577563 /drivers/net/wireless/ath/ath5k/reset.c
parentf00643888ca435ce6934482243733cc140281d10 (diff)
ath5k: disable 32KHz sleep clock operation by default
While 32 KHz sleep clock might provide some power saving benefits, it is also a major source of stability issues, on OpenWrt it produced some reproducible data bus errors on register accesses on several different MIPS platforms. All the Atheros drivers that I can find do not enable this feature, so it makes sense to leave it disabled in ath5k as well. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Acked-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/reset.c')
-rw-r--r--drivers/net/wireless/ath/ath5k/reset.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index 0e89fc9a75a..9f9c2ad3ca6 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -1287,11 +1287,16 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
ath5k_hw_dma_init(ah);
- /* Enable 32KHz clock function for AR5212+ chips
+ /*
+ * Enable 32KHz clock function for AR5212+ chips
* Set clocks to 32KHz operation and use an
* external 32KHz crystal when sleeping if one
- * exists */
- if (ah->ah_version == AR5K_AR5212 &&
+ * exists.
+ * Disabled by default because it is also disabled in
+ * other drivers and it is known to cause stability
+ * issues on some devices
+ */
+ if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
op_mode != NL80211_IFTYPE_AP)
ath5k_hw_set_sleep_clock(ah, true);