diff options
| author | Rajkumar Manoharan <rmanohar@qca.qualcomm.com> | 2011-11-22 18:52:00 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-11-28 14:36:22 -0500 |
| commit | a261f0e965b7e903873880cec1a70c9cbc776c76 (patch) | |
| tree | a97b242f5c58bdd7be622ea72d21cbaa3fb2fa3f /drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | |
| parent | 4eb287a4048e4a2cb0400a6d972d97739ec8c799 (diff) | |
ath9k_hw: Fix minimum CTL power for each runtime mode
The conformance test limits (CTL) for each regulatory domains
(FCC/ETSI/MKK) are programmed for each runtime modes (11B,11G,
HT20 and HT40) in EEPROM. The lowest ctledge power value of a
particular running mode should not be used while computing
ctledge power for a different running mode.(i.e 11G's min ctledge
power should not be used while computing ctledge power for HT20).
Currently, the code does not handle this properly which would
result in incorrect txpowers in certain cases. So reset the
twiceMaxEdgePower to the default while computing min ctlegepower
for every mode.
Cc: David Quan <dquan@qca.qualcomm.com>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_eeprom.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index a93bd63ad23..4ba6f52943a 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c @@ -4779,7 +4779,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, { struct ath_common *common = ath9k_hw_common(ah); struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; - u16 twiceMaxEdgePower = MAX_RATE_POWER; + u16 twiceMaxEdgePower; int i; u16 scaledPower = 0, minCtlPower; static const u16 ctlModesFor11a[] = { @@ -4880,6 +4880,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, ctlNum = AR9300_NUM_CTLS_5G; } + twiceMaxEdgePower = MAX_RATE_POWER; for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { ath_dbg(common, ATH_DBG_REGULATORY, "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", |