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author | Wey-Yi Guy <wey-yi.w.guy@intel.com> | 2010-06-24 13:18:33 -0700 |
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committer | Wey-Yi Guy <wey-yi.w.guy@intel.com> | 2010-07-02 11:10:15 -0700 |
commit | 947279eefb77f79015a79b032eb825a065ab035f (patch) | |
tree | 4e1549413c68b46e1091b7297350fb014e1edc43 /drivers/net/wireless/iwlwifi/iwl-commands.h | |
parent | ad8d8333b12d46f26093eab796cb309ec1a1f5f9 (diff) |
iwlwifi: tx fifo queue flush command
Add host command and structure for tx fifo queue flush
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-commands.h')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-commands.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h index a304f771bcc..b28cb4ffedc 100644 --- a/drivers/net/wireless/iwlwifi/iwl-commands.h +++ b/drivers/net/wireless/iwlwifi/iwl-commands.h @@ -97,6 +97,7 @@ enum { REPLY_ADD_STA = 0x18, REPLY_REMOVE_STA = 0x19, REPLY_REMOVE_ALL_STA = 0x1a, /* not used */ + REPLY_TXFIFO_FLUSH = 0x1e, /* Security */ REPLY_WEPKEY = 0x20, @@ -1209,6 +1210,39 @@ struct iwl_rem_sta_cmd { u8 reserved2[2]; } __attribute__ ((packed)); +#define IWL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0)) +#define IWL_TX_FIFO_BE_MSK cpu_to_le32(BIT(1)) +#define IWL_TX_FIFO_VI_MSK cpu_to_le32(BIT(2)) +#define IWL_TX_FIFO_VO_MSK cpu_to_le32(BIT(3)) +#define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00) + +/* + * REPLY_TXFIFO_FLUSH = 0x1e(command and response) + * + * When using full FIFO flush this command checks the scheduler HW block WR/RD + * pointers to check if all the frames were transferred by DMA into the + * relevant TX FIFO queue. Only when the DMA is finished and the queue is + * empty the command can finish. + * This command is used to flush the TXFIFO from transmit commands, it may + * operate on single or multiple queues, the command queue can't be flushed by + * this command. The command response is returned when all the queue flush + * operations are done. Each TX command flushed return response with the FLUSH + * status set in the TX response status. When FIFO flush operation is used, + * the flush operation ends when both the scheduler DMA done and TXFIFO empty + * are set. + * + * @fifo_control: bit mask for which queues to flush + * @flush_control: flush controls + * 0: Dump single MSDU + * 1: Dump multiple MSDU according to PS, INVALID STA, TTL, TID disable. + * 2: Dump all FIFO + */ +struct iwl_txfifo_flush_cmd { + __le32 fifo_control; + __le16 flush_control; + __le16 reserved; +} __attribute__ ((packed)); + /* * REPLY_WEP_KEY = 0x20 */ |